[SOLVED] Stability Simulation with Cadence

Dear friends,

Some friends suggested me to use the stability analyses from cadence to get the AC parameters of my amplifier (DC gain, GBW, PM)

The simulation setup is as I attached it below, as you can see that the circuit is provided only with DC, then I run the STB simulation and using the Iprobe as the instance. After running the simulation I can get all the required parameters,

My question here, when I measure the AC parameters from the open loop gain (the classical simulation setup) I have to be very careful to compensate for the input offset voltage, otherwise my setup can easily fail,
However from the STB analyses I can see it is closed loop feedback so I think there is no need for warring about the offset voltage compensation,

Please confirm me if it is right,

Such a property is very important for me when I want to simulate the DC gain over the entire range of the input common mode voltage. Such kind of simulation if I would perform by using the classical open loop setup it will not be accurate because the offset voltage also can change with the input voltage range.

My second question please, Does the STB result has good accuracy and can it be depended ?

Thank you very much in advance

If your "classical simulation setup" depends on offset voltage, it's an impractical method that has nothing in common with usual measurement methods. STB is a practical tool to ease the simulation setup, the same result can be achieved with classical methods like Middlebrook or approximately an open loop setup with DC bypass.

Dear FvM,

Every open loop simulation is very sensitive to the input offset voltage and therefore I must consider to compensate it to be sure that my amplifier is in the active region, the sensitivity to the offset voltage become more considerable if I am simulating very high gain amplifier. I believe you agree with this,

But please FvM I was asking of confirmation if the STB is closed loop simulation in which I should not wary about the offset voltage.

I have one more question for you please,
After I run the STB and plotted the gain in dB, I wanted to save the DC gain value in to my calculator, usually I do by going to the signal and apply the function of (Ymax) then I save the value of it in to my ADE so I can read the value directly every time I run the simulation.

However, I was not able to use the function of (Ymax) with the result coming from the STB analyses, is there a solution of it or there is other method

Thank you once again

You have to use the getData function, like this way:
ymax(db20(getData("loopGain" ?result "stb")))
This is just example, not guaranteed to work instantly, so to get the valid expression I recommend to use the Direct Plot menu -> Main Form. Choose open loop gain, tick 'Add plot to outputs' and click on OK.
It will add the exact function to the outputs where you can easily add the ymax() function around the valid expression.
Help to Direct Plot window on page 23: https://www.lumerink.com/courses/ece515/Handouts/Opamp Design and Simulation.pdf

Thank you frank for your reply

I will try this tomorrow and I hope it will work.

Please I have three related questions:

1. about the position of the Iprobe in my simulation setup image. Can the direction of the Iprobe affect the simulation ?

2. What if I put the probe just directly at the output of the Op-amp as seen below.

3. Is it mandatory to simulate the STB under the unity gain configuration or it can be the same at any gain value

Thank you very much in advance

First, about your offset question. You have a setup where the amplifier is in a feedback configuration and as with any other feedback topology, it will try to achieve virtual short between the two inputs of the amplifier (to the extend allowed by your loop gain). So, if you keep your input at 1.65V DC, you can imagine that there is an additional voltage source in series with the 1.65V voltage source that accounts for the offset of the amplifier referred to the input. Given the virtual short at the inputs of the opamp, the output of the amplifier will settle at the 1.65V+/-Voff. And that's all. There is a feedback which will not allow the opamp to rail. It is not like simulating the amplifier open loop. And that's exactly the reason why you simulate stability by breaking the loop in ac but keeping the loop closed for DC. This is part of what the iprobe in cadence does. Actually, that iprobe is implementing a modified version of the Middlebrook method for simulating stability.
Now, with your setup you can sweep the input voltage and test stability for the entire range you're interested in and you should not much worry about offset.
Yes, the stb results are reliable for small signal stability. You can place the iprobe anywhere in the loop and it should give you the same results, unless by moving it you start disturbing other loops in the system. Direction of iprobe does not matter for stb simulation.
You should simulate your stability in the feedback configuration you intend to use. Stability is worst in unity gain configuration. But then, in unity gain configuration your loop gain is equal to the open loop gain of the opamp itself since your feedback factor is 1.
If you want to get the value of the DC gain from the stb simulation why don't you put the db20 of the loop gain in the calculator and click on the "value" function, then interpolate at some low enough frequency where your DC gain is still constant with frequency?

1, No, iprobe direction doesn't matter. stb analysis in cadence uses Tian's method, similar to Middlebrook but direction matters only at Middlebrook.
2, It is fine, you can break the loop at different places, your last choice shouldn't affect the result. Check more cases to learn, where you get else behaviour we can discuss about that why you got.
3, Obviously the feedback network can modify the open loop gain parameters. For example imagine a unity gain buffer as on your figure, and after stb analysis you get A0 for the DC gain. Now change it and add 2 resistors to form an inverting amplifier with gain=-1, as this: https://www.electronics-notes.com/images/op-amp-inverting-amplifier-01.svg
The feedback network has a Beta factor =R1/(R1+R2)=0.5 which reduces the DC open loop gain to A0*Beta=0.5*A0. Because of this the unity gain bandwidth will be halved too, but Phase Margin and Gain Margin can be higher compared to unity gain buffer configuration, but not unconditionally...
With higher closed loop gain values you can see the Beta factor will decrease more, and the DC open loop gain, unity gain bandwidth will follow that.

Dear friends,

I am deeply thankful to your help and suggestion,

now my setup is working very fine, now I can apply mathematical expression to my loop gain stability data,

The solution as was suggested by freank, by using Result--Direct plot from-- then I get this image below where I can choose what I need to plot.

I could save the value of DC gain using the expression ymax to my gain graph, also I could apply the expression of unity gain frequency and save the value to my ADE interface,

There is only one expression is not working with me, that is the phase margin.. I could read the value from the stb snalyses but the thing I want to save it to me ADE.. so when I go to the loop gain graph in magnitude and apply the PhaseMargin function the result is not coming true, it only shows 180.

is there other method to get the phase margin reading and save it to my ADE.



Thank you very much for your help

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right now I repeated the simulation setup and used AC source instead of the Iprobe. the source setting is: AC magnitude =1 V, and the DC voltage = 0V.
The simulation is giving me exact value of the Iprobe method when I run the STB simulation.

However if I do the transfer function manually from the AC simulation it is not giving me the same value of the Phase margin,, Does it mean that the most accurate setting is to test it from STB if you had similar case ?

Note I have reversed the polarity of the source used as a probe and the result is not affected so I would confirm that is just exactly like the Iprobe, doesn't care about the source polarity

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Updated

Dear friends, I found a solution for the phase margin record,
when I run the parametric analyses after then from Direct plot window : Phase Margin plot...... it give me the PM over the entire range of sweep

I deeply thank you for this type of simulation, its made my design easier ,,,

Dear friends,

I finished reading the article from frank, it was really helpful

I have one question about the simulation he perform for the CMFB loop, he use two dfstbprobe,

in our other discussion (given by similar post) you have suggested me to use the MiddleBrook or the Iprobe to break the CMFB loop

I have attached you below my two setup, please which of them should be the right setup

in the first setup the differential amplifier is connected in closed loop configuration while in the second one is in open loop,

your other suggestion is always welcomed and highly appreciated,,,, again I am sorry the system is limiting my number to vote for help... is there a limit for it ?
Thank you in advance

Setup 1 is the correct. Setup 2 is not realistic, it eliminates input parasitic capacitance, it doesn't apply feedback network, however fully diff. OPAmp always use feedback network to create linear, controlled and stable closed loop gain. You cannot use the 2nd setup as normal amplifier, max for comparator, but it should be an OPAmp I suppose.
...and try diffstbprobe from analogLib, some people say it is more reliable than cmdmprobe and iprobe is not mentioned. I am sure iprobe is the best for single ended circuits, but for fully differential...I don't know.

Of course, as frankrose said, setup 1 is the correct one. For the CMFB loop you don't need to use diff probe, iprobe is enough.

Can you also show your amplifier + CMFB circuit (transistor level).

Thank you my dear friends for your answers and your kind help,
Below is my circuit,,, I draw it with Visio, image I get from Cadence for circuit is not at all clear, I don't know why such giant companies like MentroGraphic or Cadence they don't care for the circuit print out quality..



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Here you see the CMFB circuit I am using

I am controlling half of the CMFB required voltage and the other half is fixed by the biasing circuit.. this scheme is supposed to give me good CMFB loop stability ( although I didn't test it yet). Regardless this scheme would reduce the closed common mode gain to half (as my diode load error amplifier gain is about one), however the loop gain is still high.. I can prove it by the error I am getting from the VCM at the output which only 8 mV different from the required voltage 1.65 V.



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Dear friends now I go back to the differential stability simulation,

are the two setup below in the image are right ? please confirm it to me. is there any other special setting in the simulation I must do when using the diffsgtbprobe ? or it is the same as with Iprobe.

as far as I understood from the Iprobe or the middlebrook it is only a zero voltage DC voltage with ac magnitude, it means it is open for ac but short for DC and hence we can put any where in condition it should break the whole loop



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Dear friends I came with two other ideas for testing the closed CMFB loop which you can see below, in the first one is based on the idea of diffstbprobe and the other one is an extension of using the Iprobe,,, please see it and tell me your kind opinion about it

I think the M1 and M2 in your CM transistor circuit should be PMOS, not NMOS as you have drawn it.

For the differential loop stability, it shouldn't matter where you put the diff probe. I would personally prefer your setup 1, but the other one should also work. Middlebrook method doesn't only inject voltage in the loop, it also injects current and thus finds two loop transfer functions and then combines them.
For the CMFB stability setup, you don't need to use diff probe there, you can do it with just ibrobe as in your setup 2, or you can also place the iprobe at the output of the CMFB amplifier, which will be what I would do.

I see from your transistor level schematic that you have a two stage amplifier and you measure the CM at the output and feed it back to the input stage. Here is a question for you. If you think about the common-mode, not the differential mode signals, what is the polarity of the two stages in your main amplifier? Are they inverting or non-inverting with respect to common mode?

Middlebrook method doesn't only inject voltage in the loop, it also injects current and thus finds two loop transfer functions and then combines them.

Click to expand...

In the general case, yes. In simple case e.g. the discussed CMFB loop, you get away with voltage transfer function only https://www.edaboard.com/showthread...plifier-loop&p=1643117&viewfull=1#post1643117

For the CMFB stability setup, you don't need to use diff probe there, you can do it with just iprobe as in your setup 2, or you can also place the iprobe at the output of the CMFB amplifier, which will be what I would do.

Click to expand...

Does diffprobe provide a common mode gain? Otherwise it will not even work in this place.

Dear Suta,

Thank you very much for your reply,
yes you are right by mistake I draw M1&M2 as NMOS, they are actually PMOS.

Coming to the next point, I agree with you completely that we don't need a diffstbprobe to simulate the CMFB loop, one Iprobe should do the same work, I only got confused about it when I read the attachment by frank, there he use two diffstbprobe as I also shown it below.

For the common mode polarity, the CMFB amplifier is working by this way, when the output common mode increasing it decreases the VCMFB voltage and I am getting good control result with this connection.



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Thank you FvM for your reply,

you asked suta ''Does diffprobe provide a common mode gain? Otherwise it will not even work in this place.'' but actually he was talking about using the Iprobe not the diffstbprobe

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Let me please summarize our discussion here,

for the differential mode characteristics I will use the diffstbprobe (as given by setup 1 or 2 of my differential simulation setup).

for the CMFB loop characteristics I will only use one Iprobe at the output of the CMFB amplifier (common sense amplier) as shown in the setup 1 image of simulating the common mode.

FvM and Junus, diffstbprobe has a variable where it can be set to simulate differential stability (variable=1) or common mode stability (variable=-1). You can simulate everything with diffstbprobe. Name is confusing, diff means "differential circuit probe", and not "differential stability probe". Earlier the probe name was 'cmdmprobe' in the analogLib, means "common mode & differential mode probe", but Cadence developed it to diffstbprobe which is more reliable.

Dear frank
Dear all Mentors

I just simulated the differential characteristics of my differential amplifier, I put the diffstbProbe at the two outputs and I run the stability simulation, results are coming fine as you kindly see below,

However, I just saw the comment of frank about the setting of the diffstbprobe to be +1 or-1,, in the cadence I use there is no option to enter this values, kindly I attached you the image of this probe properties... but I think this setting was only valid for the old probe of cmdmprobe.

Please I would like to confirm the result I am getting, is is ((Vo+)-(Vo-)) / ((Vin+)-(Vin-)) or it is the gain given with respect to only one output, if so then I have to multiply it with 2.
Why I am suspecting it because in my single ended amplifier based on the same amplifier I was getting DC gain = 93 dB while here is 90 dB... the 3 dB difference it making me thinking I am simulating the half of the gain

Junus2012 said:

However, I just saw the comment of frank about the setting of the diffstbprobe to be +1 or-1,, in the cadence I use there is no option to enter this values, kindly I attached you the image of this probe properties... but I think this setting was only valid for the old probe of cmdmprobe.

Click to expand...

Not on the symbol properties you can set this variable, you have to set at the stb analysis that differential or common mode simulation you need. But in the netlist you should see the variable value (+1,-1).

Dear Frank,

I can see it now, I also attached the image of it.

I am just wondering, if I change the setting to common does this mean that the same circuit setup will be able to determine the CMFB loop characteristics ? or it does mean I have also to put the diffstbprobe in the CMFB loop as well,

No, that doesn't make sense to put diffstbprobe to else place. Leave it there where you wanted originally on your figure, setup 1 or setup 2 is good too. And go through the pdf of Idaho university, very detailed.