Oct 31, 2017 #1 C cmos_ajay Full Member level 2 Joined Jan 30, 2007 Messages 126 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,296 Activity points 2,247 Attached is a constant gm bias circuit (gm = 1/R ) There are 2 loops in this circuit. Where should i cut the loop to check stability in Cadence ? Attachments gm_R.JPG 105.3 KB · Views: 161
Attached is a constant gm bias circuit (gm = 1/R ) There are 2 loops in this circuit. Where should i cut the loop to check stability in Cadence ?
Oct 31, 2017 #2 erikl Super Moderator Staff member Joined Sep 9, 2008 Messages 8,108 Helped 2,695 Reputation 5,370 Reaction score 2,308 Trophy points 1,393 Location Germany Activity points 44,123 Re: stability - cmos constant transconductance bias ? Always cut a loop between a low impedance output and a high impedance input (so you won't change the output load too much). To check the impact of both the positive and negative feedback loops at the same time, cut directly at the output of the amp:
Re: stability - cmos constant transconductance bias ? Always cut a loop between a low impedance output and a high impedance input (so you won't change the output load too much). To check the impact of both the positive and negative feedback loops at the same time, cut directly at the output of the amp: