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[SOLVED] Stability - CMOS constant transconductance bias ?

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cmos_ajay

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Attached is a constant gm bias circuit (gm = 1/R )
There are 2 loops in this circuit.
Where should i cut the loop to check stability in Cadence ?
 

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Re: stability - cmos constant transconductance bias ?

Always cut a loop between a low impedance output and a high impedance input (so you won't change the output load too much).

To check the impact of both the positive and negative feedback loops at the same time, cut directly at the output of the amp:constant-gm-bias-circuit.jpeg
 
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