Speed Binning using Path Delay Testing

[Prithvee]

Hi,

I would like to know why the least timing slack paths are chosen for path delay testing to bin the ICs according to their speeds/performance.
Is it because low timing slack paths are close to the functional frequency(speed) of the IC? Please explain.

Thanks.

 

[pavanks]

See while calculating the min clock period we have to consider the max worst path. As the path carries data which requires this much time to put it to the output. If u dont meet this then u cant get the expected output.

So always the worst negative slack is considered for the performance. So if u dec ur worst setup ur inc ur performance.

hope it helped.

 

[Prithvee]

Thanks Pavan. I would also like to know about latch to latch path tests.

Thanks in advance.

 

[pavanks]

Thanks Pavan. I would also like to know about latch to latch path tests.

Thanks in advance.

The latch also has setup and hold time which u need to meet.
But we dont use latches as they produce glitches.

 

[Prithvee]

Can you explain more on that? Cos I would like to know whether latch to latch path tests go thru custom mermory arrays.

Thanks