THe Good and Powerfull feature a particlar simulation or at test case can simulated with rand seed which is used while exdcuting the test. In a regression u can write a loop a particular test for 5 - 10 times with diferent random seed and it produces different random values for the filed and some times u can catch some corner errors . Vera also has randmization but not powerfull enough as specman
system C is promising.
But the verification plan is more important than the language you use.
I use verilog and C and python.
in the future, I will choose system C
I don't think vhdl have the same bright future as system c and system verilog. Because as I know, most eda companies support vhdl less than before. I am afraid that this language will die soon.
it might be system C , the best simulation lang for a soc verification might be System C, but do anybody have some few good reasons for supporting the above statement? I believe that it is basic feature i.e the transaction level modelling might be used.