SoC system level simulation

[Arnold]

system verilog is just a dream at this stage.

 

[manaman]

We adopted specman for verification tool.

And it found some bugs which couldn't find on logic simulation and fpga board test.

However it's so difficult..

I hope Specman user will change good information in this forum...

Do you mean specman at system levlel AFASIK it is a tool for ip level verification , can u share some more details

Added after 2 minutes:

We adopted specman for verification tool.

And it found some bugs which couldn't find on logic simulation and fpga board test.

However it's so difficult..

I hope Specman user will change good information in this forum...

Do you mean specman at system levlel AFASIK it is a tool for ip level verification , can u share some more details

 

[sarath51]

THe Good and Powerfull feature a particlar simulation or at test case can simulated with rand seed which is used while exdcuting the test. In a regression u can write a loop a particular test for 5 - 10 times with diferent random seed and it produces different random values for the filed and some times u can catch some corner errors . Vera also has randmization but not powerfull enough as specman

 

[Kulprashant]

hi,
you can use systemc and psl/sugar for soc verification.

with regards,
kul.

 

[wkong_zhu]

system C is promising.
But the verification plan is more important than the language you use.
I use verilog and C and python.
in the future, I will choose system C

 

[Arnold]

I also use verilog/python/psl currently. The future is not clear. I hope specman can be the winner.

 

[JesseKing]

I think systemverilog and VHDL 200X will be the future.

I don't think vhdl have the same bright future as system c and system verilog. Because as I know, most eda companies support vhdl less than before. I am afraid that this language will die soon.

 

[soccer]

I think system verilog is the most useful tool in future. Nowday, system C and C/C++ is used.

 

[power-twq]

The most popular simulation language is verilog and pure c.

Hi, guys

what's the most popular system level simulation and verification language for the industrial SoC design? SystemC, pure C or system Verilog.

Many thanks,

 

[eeeraghu]

it might be system C , the best simulation lang for a soc verification might be System C, but do anybody have some few good reasons for supporting the above statement? I believe that it is basic feature i.e the transaction level modelling might be used.