SoC system level simulation

[zhanch]

Hi, guys

what's the most popular system level simulation and verification language for the industrial SoC design? SystemC, pure C or system Verilog.

Many thanks,

 

[sarath51]

comination of systemc , C++ , C verilog

 

[eexuke]

Currently I am using systemC....However,maybe systemverilog is better for a hardware designer than systemC.

 

[rprince006]

It is said that system_verilog is good for modeling, design and verification purposes. However, it is not widely used in the moment.

 

[bigyellow]

I think systemverilog and VHDL 200X will be the future.

 

[zhanch]

comination of systemc , C++ , C verilog

Is that the way for industrial project?

 

[sarath51]

This is with refernfece to the System Level verification for a SOC project i have been invloved with .Verilog- had few verilog test bencbes and test code , C programs for emulating the embedded sotware , System C models are reference models for checking the functionality

 

[zyphor]

have you tried specman E or vera?

 

[bkat]

i thk system_verilog is better.

 

[sarath51]

Specman E makes the Simulations slower , its main advantages lies in design with switching and bridging charctersitcis. system verilog is not matured enough or not all tools are supporting all the constructs required for verification

 

[omara007]

big percentage of companies do use Matlab or C/C++ in their System level simulation .. then go from matlab to HDL manually ..
Currently , some companies went for SystemC .. which is basically C++ with some added libraries .. no more no less .. the same structure ... the same compiler .. the same everything .. but with some new interface that looks like HDLs ..

The good about SystemC is that many HDL simulators started supporting it .. like ModelSim for example .. plus it's already free to download it ..
You can also use the common free compilers (like GCC) for compiling SystemC .. which is professional enough to give u good results .. and widely used in the industry .. it originally comes for free when u install ur linux redhat for example ..

 

[Arnold]

How about Cadence's CVE? any success story?

 

[Alvinnju]

I think verilog

 

[sxg]

i think system c is good.
For the hardware and sofware designed on the same platform ,it will
reduce the Time to Market

 

[stocking]

I think systemC is more powerful!!

 

[hanm]

Yes,system C is the better one,I think.

 

[wicho]

We adopted specman for verification tool.

And it found some bugs which couldn't find on logic simulation and fpga board test.

However it's so difficult..

I hope Specman user will change good information in this forum...

 

[Arnold]

what you mean here about the diffculty of using specman? slow in building the test environment or a very long learning curve or ...?

I think Specman E can help to deploy a test environment very fast, whereas building a test environment in SystemC will be a much slower process. Specman E testing program can be executed without compilation, this is a very useful feature for HVL.

 

[wicho]

As a newbie for specman, it's too long learning curve...

And it's difficult to build test environment...

If you are a expert, this is no matter...

And there are not data it will be able to refer...

Vault is only reference site..

If someone share reference data(real verification project), it's so helpful to newbie..

 

[feel_on_on]

i think system verilog better to verify this level simulation!