Slew rate simulation of a discrete Op amp on Ltspice

[PorDeseign00]

Hello everyone.

I have a problem with the simulation of the slew rate of a two-stage op amp on Ltspice..

When I configure the op amp as a unity gain buffer the simulation goes into an infinite loop and I can't see the response speed of my op amp. when I connect the square wave pulse to one input terminal Vin+ of the op amp and connect the other to gnd without carrying out the feedback, I can measure the slew rate, but I don't think it's the right method.

Thank you so much!!

 

[D.A.(Tony)Stewart]

There must be a large imbalance in charge, Q for the M1, M2, M3, and M4 drivers to cause more asymmetry. It is more obvious with C2 removed. I could see no obvious way to balance it. It seems in the overdrive case, things become rather non-linear and unbalanced.

 

[PorDeseign00]

so having a charge imbalance there will be different charge/discharge switching times regarding capacities. Perfect, thank you very much! but if the currents are perfectly balanced at 30mA on the differential amplifier, how is it possible that there are unbalances? I'm thinking that they are due to the parasitic capacitances of the MOS in question...

 

[D.A.(Tony)Stewart]

It looks better in linear mode. GBW = 389 MHz = 100 * 0.35 / 90 ns , SR = 400mV/90 ns

--- Updated Jun 30, 2024 ---

Correction: The asymmetry seems to be a bug in LTspice with the duty cycle of 1us / 2us being wrong.
This is the VD1 = AC1 pulse gen. node PULSE(-2m 2m 0 0 0 1u 2u 10)

Or is it a bug in my understanding of LTSpice with 5% slopes added when 0 was specified?

where 0.91 / 2 us pulse comes out as 1.0 / 2.0 us
View attachment 191972

Why the asymmetry in the pulse gen?

Precompensated duty cycle

 

[D.A.(Tony)Stewart]

Discovery
After reading the .log file, LTspice automatically adds a rise time of about 10% a fixed number in ns whichever is smaller, presumable to prevent division by zero for currents. Thus the duty cycle will become asymmetrical for high-frequency square waves unless you realize how to create the ON time by adding 10% to the period = Trise_fall or something close to this. This makes it difficult to specify perfect 50% duty cycle Pulses >= 10 MHz.

PULSE({Vi} {Vf} {Tdelay} {Trise_fall} {Trise_fall} {Tperiod/2+Trise_fall} {Tperiod})

- where Trise_fall when specified to 0 will become ~ 10% of Tperiod for very short periods in ns or us.

In the previous example, I subtracted 15% of Tperiod to the value after Tf to obtain close to 50% from sig. gen.

Whereas, LTspice help says nothing about adding 10%Tperiod to Tr=0, Tf = 0.

"PULSE(V1 V2 Tdelay Trise Tfall Ton Tperiod Ncycles)"

 

[PorDeseign00]

Hello!!Is there a way to decrease the output impedance of this amplifier?? I noticed that it has an output impedance of about 990 ohms and I would like to reduce it. I know it is possible to use a buffer to match the impedance, but I would like to know if there are other methods as well. Thank you very much!!

 

[D.A.(Tony)Stewart]

The common effects of forward current gain gain and negative feedback are 2 options. Either Class A or AB followers for BJTs CMOS buffers need gain stages with NFB and low current to prevent shoothru.

 

[BradtheRad]

This circuit is in unaltered form from the menu of Falstad's animated interactive simulator. '741 current limits'. It shows the internal circuitry. I guess it's correct more or less.

The output stage is a half-bridge through 25 ohms in one emitter leg, 50 ohms in the other polarity. The differential detector is one part of the op amp. The rest of the circuitry appears to amplify so the load receives a mathematically correct voltage, whatever is the load resistance. The load can be a few hundred ohms. If we try lesser resistance then it burdens the output stage.

Related circuits in the menu are 741 slew rate, 741 internals, 741 inverting amplifier. Notice the 30 pF capacitor near the middle. Raising its value slows the slew rate. We can assume the slew rate is influenced by further contributing factors as mentioned in this thread.

falstad.com/circuit

Toggle full screen under File menu.

 

[danadakk]

"Typical" Zout of a OpAmp, leads to question

I noticed that it has an output impedance of about 990 ohms and I would like to reduce it.

So reduce to what value and at what frequency @ what Gclosed_loop?


Regards, Dana.

 

[PorDeseign00]

How can I calculate the total consumption of the device in my ProveDiff schematic? I looked for some Spice guides but I didn't find anything in the case of multi-stage Op amps.. I don't think it's enough to calculate W=VDD*Id. I should see how much current my input circuit absorbs... could anyone answer me? A thousand thanks!

--- Updated Jul 2, 2024 ---

"Typical" Zout of a OpAmp, leads to question

View attachment 192010



So reduce to what value and at what frequency @ what Gclosed_loop?


Regards, Dana.

for example adapt the output resistance to a load in the order of tens of ohms (for example to an 8 ohm resistive load, a talking car...), therefore to an audio frequency for example... Thank you so much!!

 

[D.A.(Tony)Stewart]

Pressing control key with the mouse over will change the icon for power and then click, and you can display watts for any component, including the power supply

 

[PorDeseign00]

Pressing control key with the mouse over will change the icon for power and then click, and you can display watts for any component, including the power supply

Perfect! so for example if I want to see the consumption of the differential stage I just need to see the consumption of each MOS in question and do the sum..

 

[BradtheRad]

100 mA is a frequent round figure for small speakers producing audio. Often on spec sheets, and also I've measured about the same average. The 386 IC is represented in schematics as an op amp. Spec is less than a watt.

 

[PorDeseign00]

Greetings!In my schematic with a bias current of 100mA, dual power supply +/-5V and a Miller capacitance of 150pF I obtain a bandwidth of approximately 5.2Khz. I know that the Miller capacitance helps to form the dominant pole, but I wanted to know if there is any technique to increase the bandwidth... I know that the MOSFETs I'm using 2N7002 and BSS84 are power mos, so the bandwidth can't be that great,I realize that parasitic capacitances do their job... Could anyone tell me if it is possible in my schematic to increase the bandwidth from 5.2KHz to a higher value while maintaining a discreet stability margin? Thank you so much!!

 

[danadakk]

Possibility :

Using Cascade Topologies to Beat the Miller Effect in Semiconductor Switches

Resistors, capacitors and inductors will continue to be challenged because of, well, the law of physics. There’s nothing we can do about the challenges, so electronics designers have, since the days of thermionic valves, learned to work around these factors by developing clever circuit...

www.qorvo.com

Regards, Dana.

 

[PorDeseign00]

Possibility :

Using Cascade Topologies to Beat the Miller Effect in Semiconductor Switches

Resistors, capacitors and inductors will continue to be challenged because of, well, the law of physics. There’s nothing we can do about the challenges, so electronics designers have, since the days of thermionic valves, learned to work around these factors by developing clever circuit...

www.qorvo.com

Regards, Dana.

A thousand thanks!! I tried but I lose a lot of gain... more than the differential stage alone offered me

 

[PorDeseign00]

Hi everyone, how can I implement a common source cascode stage in my ProveDiff schematic? A thousand thanks!!

 

[D.A.(Tony)Stewart]

Use your understanding of Kirchoff and MPT to bias for maximum voltage gain or power gain with impedances.

 

[PorDeseign00]

Use your understanding of Kirchoff and MPT to bias for maximum voltage gain or power gain with impedances.

I did it, the MOS results in polarization from .OP ,but the cascode common source doesn't amplify me. remains more or less the same amplification of the differential about 43dB, in the output from the cascode stage I have 42dB. Also attenuates..

 

[PorDeseign00]

I did some tests and this is the best result I got... a bandwidth of around 42Khz (compared to the 5.2Khz I had previously). I saw from the datasheet that the 2N7002 device appears to be in saturation for a VGs=5V and an ID=50mA therefore I opted for the solution in the schematic by creating an additional current mirror with an NMOS device. The only fact is that the open loop system is unstable since at unit gain the phase is approximately 209° (they are unstable for approximately 30° above)... If I introduce the miller capacitance to compensate the system the bandwidth is reduced and I know this... is there some additional technique that allows me to maintain a good bandwidth and maintain a decent phase margin ?? thank you very much!! Attached is the ltspice schematic(AMP_MULTISTAGE) and a screenshot of the test I had previously done with load resistor and nmos cascode bias with Vgs

 

[PorDeseign00]

Could someone kindly help me please? I can't get out of it