Slew rate simulation of a discrete Op amp on Ltspice

PorDeseign00

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Hello everyone.

I have a problem with the simulation of the slew rate of a two-stage op amp on Ltspice..

When I configure the op amp as a unity gain buffer the simulation goes into an infinite loop and I can't see the response speed of my op amp. when I connect the square wave pulse to one input terminal Vin+ of the op amp and connect the other to gnd without carrying out the feedback, I can measure the slew rate, but I don't think it's the right method.

Thank you so much!!

 

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Hi,

"I don´t think ..."
There are many documents that describe how to do slew rate tests. Many OPAMP manufacturers provide them.

I recommend to read through some of them, find out what is suitable for your test and what is not suitable.
Then setup the test conditions ... and run the test.

Best is to write down / sketch what you expect before you perform the test. This way you will be more critical about the result.

Klaus
 
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the problem is that I don't have documentation because the project is mine. However, I got stuck on the slew rate simulation. thank you!
 

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When I configure the op amp as a unity gain buffer the simulation goes into an infinite loop and I can't see the response speed of my op amp
Click to expand...

Odd, any error messages or is it just hung in infinite loop ?

You seem to have a floating ground next to M2.....?
Vc+, Vc-, V6 all unconnected/floating ?

Is message dialog having a problem converging on a DC solution ?

A step response a legit way of measuring slew rate, as long as its a large signal input.

I see you are working with a discrete solution to OpAmp, of course unmatched Q's in
constant current source implementation and unmatched 7002 MOSFETs will create
a poor design. CMRR, offsets......


Regards, Dana.
 
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Slew rate is the 10 to 90 % slope in a step response.

Being a large swing it averages any variations and is always limited by the resistive current into a capacitive load, for IC's a small standard load capacitance is used. For discretes, the internal junction capacitance for Coss rises with higher conductance or lower RdsOn. Therefore the nominal RdsOn*Coss product is constant except for manufacturing variances. This correlates to the Turn-On/Off times and the RC values in your LTSPICE models.



FET components in your driver stage have typical and maximums only for RdsOn and Coss but only nominal for Turn-On and Off times.

BTW please zip your .asc file in future and include any custom settings or parameters.
Did you use the LTSpice setting "alternate" for the Engine setting vs "normal"?
 
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This is a two-stage topology. If not properly compensated, it will oscillate when you apply a pulse at its input. Your "infinite loop" is probably your transient sims trying to converge. Try to add some form of compensation to your OTA by: adding a load capacitor to the first stage, or using miller compensation. There is a lot of material on this on the web.
 
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No frequency compensation means free singing lessons.

Frequency compensation is a large determinor of slew rate.

You might (or not) find stable operation in a closed loop
A=10, A=100... setup with less comp and better reported
slew (which is a done thing, positioning test circuit to best
datasheet effect).

Open loop slew rate is also practical to measure (no osc
when things go from wound-up to wound-up by way of hard
steered front end) though it's not much use to a circuit
designer who's planning on closed loop operation and
cares about settling time foremost (yeah, you'll settle real
good when you bump into the + rail - but that's irrelevant).
 
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Slew rate may be limited by a designed current limit, resistance limit or negative feedback via the Miller capacitance. It can be any combination of these.

If you want assistance, please zip the necessary files to duplicate your problem.
 
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Thank you all for your advice and help until now!!Attached is the op amp file.Thank you
 

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  • DIY OPAMP.zip
    3.5 MB · Views: 89

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@FvM Polarity seems correct.


Negative Feedback (NFB) improves -3dB small signal linear bandwidth but not large signal Slew Rate (SR) which is limited by current output and thus output impedance and effects of dV/dt=Ic/C on Vds2 and Vgs7 then Vds7. Any linear NFB on IN- will make SR worse on large signal input .



The bipolar step input can be applied to either input. I swapped IN+/- to verify.
 
Last edited:
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@FvM was right, the first scheme I sent the configuration was not inverting.. later I corrected the scheme because I realized it and uploaded the zip file of the scheme. A thousand thanks!! Why did you connect Vout+ between R2 and R4??
 

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PorDeseign00 said:
@FvM was right, the first scheme I sent the configuration was not inverting.. later I corrected the scheme because I realized it and uploaded the zip file of the scheme. A thousand thanks!! Why did you connect Vout+ between R2 and R4??
Click to expand...
It was a CC feedback experiment. You may cut that.
 
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Hello everyone!! Out of curiosity, could anyone tell me why the negative slew rate is usually smaller in terms of variation than the positive slew rate?? For example positive slew rate 5 V/us and negative slew rate -3.6 V/us...I think it's due to the discharge times of the output capacities
 

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