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I guess it depends on the requency. More important it should be compliant to the
design rule required by technology. for setup check you normally apply slow slew rate, for hold check fast slow rate. Also some pads need slow slew rate in order not to introduce too much noise.
decision on correct slew target for clock and signal nets depends on many things. For example, the clock slew will effect setup and hold time of a flop. The signal slew will affect the delay of gate and wire, as well as noise immunity of certain circuits.
The slew rate mostly depends on your circuit style, which in turn may be technology dependent.
clock/signal slew mainly depends on ur implementation methodology and tech node.
if u target for a low transistion value, then tool will put more buff and will improve the slew rate.
and definatly slew value for a particlular lib cel depends on the tech node, as o/p slew of a cel is function of i/p slew and o/p cap value which is tech depenedent
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