Simple board Xilinx to turn on some led's

[ads-ee]

Maybe you are using an old/different version of impact while the "software" person is using a different version of ISE/Vivado. You should use the same version of tools on both ends of the process. I've noticed that there seems to be more than one IDCODE for some of their parts. Not exactly sure why they did that.

I don't recommend this but, as a test (though if you damage something it's not my fault) you could try editing the bsdl file called out in the transcript you posted.

The name of FPGA from hardware is the same with the name of FPGA from bit file, can the idcode be changed?

Name in the bit file...you mean like this?
0000030: 6e3d 3230 3134 2e33 2e31 0062 000e 7871 n=2014.3.1.b..xq
0000040: 376b 3332 3574 7266 3930 3000 6300 0b32 7k325trf900.c..2

This is a hex view from a bit file I had readily available.

 

[Vlad.]

Thank man,I solve the problem, I remove the zener diodes from Jtag conections and now it's work. Thank you. If i have other problems I will post on this topic.

 

[ads-ee]

JTAG is supposed to have pullups on the signals not zeners, unfortunately I never looked at that part of the schematic before.

You should add pullups on TMS and TCK at a minimum, to ensure the TAP SM doesn't do something random.

 

[Vlad.]

Yes, but according the documentation UG470 I need pullups on JTAG only if I use a buffer.
Corec me if I am wrong.

 

[ads-ee]

You should always pullup JTAG lines, if they float you can end up having the JTAG TAP SM go somewhere you don't want. It's a remote possibility but why run the risk.

I don't have a JTAG specification, but I think it's called out in 1149.1, though it has been decades since I read the specification.

 

[Vlad.]

Hello man, I use a Single ended clock instead a differential clock, and I was able to turn on some led's by push buttons, this was the prototype design. And next will be the final board with some minor modifications. Thanks a lot!