Signals and variables in VHDL

[TrickyDicky]

It synthesised to the logic that you describe. Things you do with variables can also be done with signals

 

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Code VHDL - [expand]
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-- use a variable to do the decode and then use that anywhere you need
-- the decode compare, this is the only kind of situation where I use variables
-- other than for modeling very large memories array (large variable arrays
-- usually simulate faster, than an equivalent variable array)
process (a, enable)
  variable decode : boolean;
begin
  -- this is done in a blocking fashion, so the if statements are only considered after
  -- decode has been assigned either with a true or a false.
  decode := a = x"2400";
  if (decode = true) then
    do_something <= do_true;
  else
    do_something <= do_false
  end if;
  -- now you can use it more than once
  if (decode = true and enable = '1') then
    some_enabled_logic <= do_enabled;
  end if
end processs;
 
-- done using a variable requires the variable assignment
-- occurs outside the process to behave the same as the
-- first example.
signal decode : boolean;
decode <= a = (x"2400");
process (a, enable)
begin
  if (decode = true) then
  .... etc
end process;
 
-- use the compare directly without an intermediate variable
do_something <= do_true  when a = x"2400" else
                do_false;

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All of the above should result in identical circuits.

 

[p11]

sorry, i couldnot follow, does that mean that we cant use variables while writing a synthesizing code. if no then its fine . but if we can write , then i want to know that how does it gets synthesized , wats the meaning of variable physically in connection to a fpga ?

 

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As you basically don't think in terms of hardware and you are don't know VHDL very well...

NEVER USE VARIABLES EVER.

 

[K-J]

wats the meaning of variable physically in connection to a fpga ?

Variables have no physical meaning in an FPGA...nor do signals. Both signals and variables are used as a method to describe functionality. A given signal or variable might end up being implemented as a specific identifiable thing in the final FPGA design...or it might not because it gets combined and optimized with other signals and variables that describe other logic. Use signals or variables, and simply understand how the language defines when they get updated. No need to try to attach physical meaning to any of it since the end result is look up tables, flip flops, memory and transistors driving fixed wiring.

None of the code is implemented exactly 'as described', instead something that is functionally equivalent is what is implemented.

Kevin

 

[vGoodtimes]

sorry, i couldnot follow, does that mean that we cant use variables while writing a synthesizing code. if no then its fine . but if we can write , then i want to know that how does it gets synthesized , wats the meaning of variable physically in connection to a fpga ?

As you basically don't think in terms of hardware and you are don't know VHDL very well...

NEVER USE VARIABLES EVER.

Perhaps a bit strong.

Variables in synthesizable VHDL must describe something that can be synthesized. Don't use variables to write programs -- no while loops. (if you get good enough at VHDL, you might be able to get very specific while loops in very specific cases to work. But don't start with the idea that while loops "just work")

Variables can be used for:
* common subexpressions -- within a process there are expressions, or parts (subexpressions) that occur frequently. These can be converted to variables and given a meaningful name.
* reduce -- similar to the verilog &x, |x, etc... These have some library functions as well, but a constant-range for loop with a variable is usually safe.
* registers (!) -- some developers will use variables for "locally declared registers". Basically, they assign the variable at the end of the process to get a something that behaves like a signal. I personally like the idea of locally declared signals (and think VHDL should allow signals to be declared in the scope of a process) but the lack of a "non-blocking" or "signal assign" on variables adds an extra level of complexity to reading the code and can introduce errors. I personally avoid this usage, but it is common enough to mention.

Variables should not be used for:
* horror (!!!) -- anytime you read a variable, write to it, and read it a second time in a process (and not in a reduction step from above). This ends up generating combinatorial logic and registers for the variable. People who do this tend to leave no comments, and this is a construct that is very prone to typos and misuse. When I see this, I _never_ think the developer was smarter than me. Avoid this as much as possible. If you must do this you should explain why. Otherwise people will re-write your code the first time something goes wrong.
* mega-horror (!!!!!) -- anytime you have while loops or loops with breaks or loops with multiplies. (usually loops with adds too). Also things where you try to do a long division, square-root, Newton approximation, or similarly complex operation IN ONE CLOCK CYCLE.

shared variables should only be used in VERY specific ways to infer RAM constructs in a way specifically described by the FPGA vendor.