rogger201
Newbie level 6
The way you wrote the shift register code won't work unless there is other code which you neglected to show that takes shift_reg and feeds it back into the input_data. Unless you show everything to do with the code all the way back to inputs and outputs of the module, we can only comment on the code you provide with your question.
This is how I have written:
Code:
parameter input_width = 8;
parameter bit_width = 1; //in this case to shift 1 bit at a time
input [input_width-1:0] input_data;
reg [input_width-1:0] shift_reg;
always @(posedge CLK or negedge RST)
begin
if (!RST) shift_reg <= input_data;
else shift_reg <= {bit_width{1'b0}}, shift_reg[input_width-1:bit_width]};
end
This is all the code thats related to this operation.