setup violation in slow corner and hold violation in fast corner in the same path

[linlinlin38]

Say you have a setup violation in a slow corner and a hold violation in the fast corner in the same path. How would you approach fixing this?

 

[dick_freebird]

Interstage delay between registers is too much. Re-register, flatter logic, pipeline, clock pullback are some options (which may or may not play, according to how many and how vigorous an infestation of Methodology Harpies in house).

 

[ThisIsNotSam]

Say you have a setup violation in a slow corner and a hold violation in the fast corner in the same path. How would you approach fixing this?

it is unlikely to have such scenario. The most critical hold path may share some logic with the most critical setup path, but there typically are cells that do not overlap. For the ones that do not overlap, traditional cell sizing optimization still applies.

 

[dick_freebird]

I've seen it, trying to do a 400MHz main clock in
0.5u CMOS. Only on the setup side, as we designed
for zero hold time in the DFFs and so hold violations
in a uniform clock field can't happen.

But "uniform" is a question, clocking with some other
could bring all kinds of kooky timing events / relations.

This could be an asynchronous design, could be in a
synchronizer / domain-crossing where such things
do happen and "expectations must encompass a
reality"? The OP leaves all that to the reader's
assumptions.

In any case, -if- timing slide is excessive, reducing
delay* between register stages is the only thing I
know, for it.

* that's from a "flop's eye perspective" - games can
be played with local clock, but you'll get very little
love from your local MHs, the customer's or their
customer's.

 

[linlinlin38]

it is unlikely to have such scenario. The most critical hold path may share some logic with the most critical setup path, but there typically are cells that do not overlap. For the ones that do not overlap, traditional cell sizing optimization still applies.

Thanks for the response, this is what I thought, but actually this was a interview question, I was curious to know what was the interviewer expecting for the answer...

 

[linlinlin38]

I've seen it, trying to do a 400MHz main clock in
0.5u CMOS. Only on the setup side, as we designed
for zero hold time in the DFFs and so hold violations
in a uniform clock field can't happen.

But "uniform" is a question, clocking with some other
could bring all kinds of kooky timing events / relations.

This could be an asynchronous design, could be in a
synchronizer / domain-crossing where such things
do happen and "expectations must encompass a
reality"? The OP leaves all that to the reader's
assumptions.

In any case, -if- timing slide is excessive, reducing
delay* between register stages is the only thing I
know, for it.

* that's from a "flop's eye perspective" - games can
be played with local clock, but you'll get very little
love from your local MHs, the customer's or their
customer's.

Thank you for the response, since this was a interview question, the scenario was actually kind of open ended. I could only think of traditional sizing/cell swapping method to address setup first until a positive margin, and then fix hold. But not sure if I'm missing anything else.

 

[ThisIsNotSam]

Thanks for the response, this is what I thought, but actually this was a interview question, I was curious to know what was the interviewer expecting for the answer...

Maybe something about CDC. Or maybe something about useful clock skew that could generate the issue in the first place.

 

[channelx43]

Thank you for the response, since this was a interview question, the scenario was actually kind of open ended. I could only think of traditional sizing/cell swapping method to address setup first until a positive margin, and then fix hold. But not sure if I'm missing anything else.

Talk about clock push at end point and overfixing setup, provided next stage has enough setup margin. Then do endpoint hold fix