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Guys,
How your are missing important point ... if Setup & hold are observed in same path, when you add buffer into the data to provide porpagation delay of 0.8 ns for fixing hold violation, the setup violation will also increased by 0.8ns.
So the effective setup violation will be 1ns after fixing hold violation & you need to increase the clock period by 1ns to fix the effective setup violation (10 + 1= 11ns). (Reduce the clock frequency = 1/11ns)
Thanks,
-Ajay