Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

setup and hold time (interview question)

Status
Not open for further replies.
h do u fix hold time violations

Good explanations ...
 

solving setup time violations

The normal thing we normally do (in most of the companies) if there is a violation of setup and hold in same path, we've to duplicate the logic and separate these two paths. This is most effective method.

-sai
 

calculate hold time, equation

sai
u r sounding out of this world

please explain how do u seperate a path into two and then do analysis on 2 different paths for setup on one path and hold on other
???????????????????????????????????
 

It's absolutely right that hold time is frequency independent.
Hold time equation, when there is hold time violation
Thd > Tclk-q + Trout + Tcombo

Hold time fix can be fixed by
a) Adding buffers in the data path after post synthesis
Thd < Tclk-q + Trout + (Tcombo + Tbuffer)
b) At the tape out level by reducing the voltage.
Voltage is inversely proportional to the delay of a design.

Note: We try to avoid fixing hold time at the synthesis level. Though DC has a command set_fix_hold to fix the hold time violation.
 

Re: setup and hold time calculation

refer the book title"static timing analysis for nanometer design:A practical approach " by J.Bhasker,Rakesh chadha.
 
Guys,

How your are missing important point ... if Setup & hold are observed in same path, when you add buffer into the data to provide porpagation delay of 0.8 ns for fixing hold violation, the setup violation will also increased by 0.8ns.

So the effective setup violation will be 1ns after fixing hold violation & you need to increase the clock period by 1ns to fix the effective setup violation (10 + 1= 11ns). (Reduce the clock frequency = 1/11ns)

Thanks,
-Ajay
 
Re: signal integrity interview question

Yes you are right dear
 

Guys,

How your are missing important point ... if Setup & hold are observed in same path, when you add buffer into the data to provide porpagation delay of 0.8 ns for fixing hold violation, the setup violation will also increased by 0.8ns.

So the effective setup violation will be 1ns after fixing hold violation & you need to increase the clock period by 1ns to fix the effective setup violation (10 + 1= 11ns). (Reduce the clock frequency = 1/11ns)

Thanks,
-Ajay

The most important thing to ask the interviewer is - DOES THIS HOLD AND SETUP VIOLATION HAPPEN ON SAME PATH OR DIFFERENT PATHS? IT CHANGES YOUR ANSWER. If same path, clock frequency needs to be 11ns. If different, then first lets fix hold on that path such that it doesnot affect setup here which is done by adding buffers on datapath closer to the pin launching the data.

Regards,
-huckle
 

Hi

I agree with Reddy's view.. We needs to fix hold violations first..
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top