settling time in folded cascade opamp

[tyd]

I still have problem for my 10-bit pipelined ADC.The digital outputs between stage1 and stage2 should be 180 degree(half clock period).But for my ADC, the differenc is one and half clock period.At first I guessed that the problem is caused by slow settling time.I Increased bias current in folded cascade opamp.But it won't work.(I am not sure if the settling time is fast for this case,becaues I used inverting confuguation to test it,it seems that there is not big change for that time).I replaced the gain stage in pipelined ADC with ideal parts.It works for high speed.But when I decreased the clock frequency,It won't work.I am not sure if it is caused by slow settling time.I also checked nonoverlapping clock,I think maybe the dead band is not big enough.I used ideal clock.It doesn't change anything.I hope I can get suggeation from expert.Thank you so much for your help.