set up and hold time, transisitor level - explanation needed

[sfriwblcii]

set up and hold time

why is set up and hold time needed ...Can anyone explain at the transisitor level as in where is this time needed going at the cmos level..is it some cap which is needing or is it some delay which is coming .....

 

[shiva_107]

Re: set up and hold time

plz find the attached slide...this explains what is setup and hold time.

 

[zic]

Re: set up and hold time

it relies to the reliability of the circuit

 

[sfriwblcii]

set up and hold time

@ shiva thanx for the pdf..... Can i find something more detailed anywhere

 

[research_vlsi]

Re: set up and hold time

GO through this book attached

Static Timing Analysis for Nanometer Designs by J. Bhasker • Rakesh Chadha

cheers

 

[nrazesh]

Re: set up and hold time, transisitor level - explanation ne

Very good document ! STA.rar !

Its a must read for everyone who is interested in STA

 

[muthamil]

Re: set up and hold time, transisitor level - explanation ne

@ research_vlsi

The STA Docs is really nice and would be very useful for everone

Regards
Muthamil

 

[denki23]

Re: set up and hold time, transisitor level - explanation ne

there are two video lectures here (i'm sorry i don't remember which ones, but they are near the end of the course) that explain timing and where setup/hold numbers come from. it is interesting to learn that of course setup and hold times are not some specific magic numbers but lie on a continuum of possibilities.

https://webcast.berkeley.edu/course_details_new.php?seriesid=2009-D-25491&semesterid=2009-D

 

[kishram4u]

see lecture 26 in webcast berkely

 

[eminem_v]

Re: set up and hold time

GO through this book attached

Static Timing Analysis for Nanometer Designs by J. Bhasker • Rakesh Chadha

cheers

Thanks for the book.. Its really a must read book for every vlsi engineer..Thanks for posting.. Keep on ticking..

 

[kumar_eee]

Good book. Thanks a lot for adding it here.

 

[jpvSoccer]

Hi,

One way to design flops is to use pass-gates to sample the D-input signal.

The pass-gate is controlled by clk and clkb.

You do not want the signal that is going through the pass-gate to be changing when the clock turns the pass-gate off.

If the signal is changing while the pass-gate is switching, what value is being passed to the MASTER latch? Who knows...could be 1, 0, or mid-level (bad).

So, to ensure this never happens timing checks are put in the simulation and sta models.

 

[jpvSoccer]

Hi, here is a cool video showing the effect of violating setup and hold time.

YouTube - Diagnosing Setup and Hold Violations

 

[ur_sagar_54]

Re: set up and hold time

GO through this book attached

Static Timing Analysis for Nanometer Designs by J. Bhasker • Rakesh Chadha

cheers

says file is corrupt.. can some one please upload it again please....

 

[Ikon]

Good book. Thanks a lot for adding it here.

I am able to download it

 

[sakthikumaran87]

https://www.youtube.com/watch?v=D7z4cMXxVGo&feature=related