josesmn
Newbie level 6
Hai all,
I have a few doubts regarding the host controller design.
From spec, its seen that the card will give "CRC OK and Busy" signal for each block write operation in a multi/single write data transfer.
How will the card give this signalling?
Thanks & Regards,
Jose
I have a few doubts regarding the host controller design.
From spec, its seen that the card will give "CRC OK and Busy" signal for each block write operation in a multi/single write data transfer.
How will the card give this signalling?
Thanks & Regards,
Jose