RS-232 Receiver and Transmitter Design in VHDL

[jleslie48]

vhdl uart receive project

There is a version of that, or comething like that in verilog too ?

I have no idea what "that" is in the above. You must avoid using pronouns in online discussions, and fully label all nouns.


"There is a version of <whatever your referring to clarified goes here>, or comething like <need a reference here to> in verilog too ?"

 

[SweetMusic]

vhdl rs-232 component

of RS-232 receiver & transmitter

 

[jleslie48]

transmit ascii via rs232 verilog

of RS-232 receiver & transmitter

look here:

https://academic.csuohio.edu/chu_p/rtl/index.html

 

[user1111]

vhdl code for transmitters

i think it will help you
https://academic.csuohio.edu/chu_p/rtl/fpga_vhdl_book/fpga_vhdl_sample_chapter.pdf

 

[zuret]

rs232 vhdl

hye all.
i'm currently working on my project involving the rs232 communication with the fpga too.the file about the step by step rs232 by Pong P. Chu is very useful.
i tried to implement it on the spartan 3e fpga but i got confused.
i dont know where the pin location for the top module except for the clk, reset, td and rd. can anybody help?

 

[friendz101]

Re: vhdl uart receiver

what's that book named ??? i need to download the other chapters... but i need to knw its name :S ??

 

[Rajul Parikh]

Hi,

Can any one send me the software tool name or link which will convert verilog code to RTL(schematic view)???

Please reply as early as possible.
Thanking you,

 

[EmbeddedDude]

Re: vhdl rs 232

The file is not there anymore. Will you please post it again.
Thanks

 

[r_moini]

Re: rs232 vhdl

hello
Can you send this rs232_vhdl.zip to me? my email is : r_moini@yahoo.com
thanks.

 

[lordgty]

Oh Sorry! some files are missing in that file. it refers to the previous chapters.
okie!!
download all chapters here.!!!

upload | ifile.it

In this chapter FF means Flag pointer for First in Fast Out Buffer.

okie
enjoy it.

The file is removed. Can u reupload?

 

[EmbeddedDude]

Very good material on VHDL code and rs232
https://academic.csuohio.edu/chu_p/rtl/fpga_vhdl_book/fpga_vhdl_sample_chapter.pdf

 

[grules]

Re: vhdl rs2323 receiver

hi
i trying to receive data from pc (matlab) to Altera de1 , but i want to see the data that i received for example to turn 8 leds ,each led = each bit in data string.
anyone have some ideas for vhdl code?
i know that data arrives to fpga( Rxd turn on on each bit)

 

[treqer]

to asynchronously receive data clock is needed

it uses a counter that displays the strobe 19 200 times per second.

counter is used to clock the high frequency (100 MHZ for example) 100m/19200=5208

counter counts up to 5208 and an overflow reset. In this next bit is fixed RXD.

to get in the middle of the stable data. - After every negative edge of the data stored in counter 2604. while counting to 5208 overflow just gets in the middle of the data

Counting 1 start bit 8 data bits, parity and stop bits coming forward to the zero bits again. t so on.

 

[mrflibble]

fpga4fun.com - Serial interface (RS-232)

 

[grules]

thanx!!!!

Now iam trying to use in same Project VHDL files & Verilog files, i saw in many forums that it possible ,iam using quartus ,is it ok?

 

[mrflibble]

Yes you can mix verilog + vhdl code in a single project.

 

[Aya2002]

The file is removed. Can u reupload?

it can be found on **broken link removed**

 

[Aya2002]

Dear Friends,

I did a Tx and an Rx for the UART_RS232 port using VHDL. It is working fine, but when I send from PC to the FPGA board, I face sometimes a wrong bits, My code is as follows: but would somebody please tell me why sometimes the data i receive inside the board are incorrect?
by the way, the code I assembled it from different codes on the internet, at the end I made good code for beginners.

Help please

-- clock divider to get the baud rate

library IEEE;
use IEEE.std_logic_1164.all;

entity clkdiv is
    generic (DIVRATIO : integer := 2500);  -- ratio by which to divide the clk: clkout = clk/DIVRATIO. Conditions: 
                                        -- if DIVRATIO is an even number, then clkout is 50% duty cycle.
                                        -- if odd, clkout is greater than 50% duty cycle
    port (
        clk     : in std_logic;         -- input clock
        nreset  : in std_logic;         -- active-low asynchronous global reset
        --
        clkout  : out std_logic         -- output clock
    );
end entity clkdiv;

architecture RTL of clkdiv is
signal clkout_i : std_logic;        -- internal clkout signal (can't use clkout directly because sometimes
                                    -- you need to read present value of clkout, and it's illegal to read
                                    -- an output port), to be buffered out to clkout port
begin
    
    -- this process implement clock divider by counter:
    -- The counter counts from 0 to DIVRATIO-1. At midpoint and end point, clkout is toggled.
    -- For example, if DIVRATIO = 4:
    -- clkout is toggled at count=1 and count=3, creating a 50% duty cycle clock, whose period equals 4 times
    -- the input clock period.
    clkdiv_proc : process (clk, nreset)
    variable count : integer range 0 to DIVRATIO-1;
    begin
        if nreset='0' then          -- initialize power up reset conditions
            clkout_i <= '0';
            count := 0;
        elsif rising_edge(clk) then
            if count=DIVRATIO/2-1 then      -- toggle at half period
                clkout_i <= not clkout_i;
                count := count + 1;
            elsif count=DIVRATIO-1 then     -- toggle at end 
                clkout_i <= not clkout_i;
                count := 0;                 -- reached end of clock period. reset count
            else
                count := count + 1;
            end if;
        end if;
    end process;

    clkout <= clkout_i;     -- buffer to output port
end RTL;



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RX is
    Port ( 
		clk,reset: in  STD_LOGIC;
--		clk_spd : IN std_logic_vector(1 downto 0);
		UART_RXD : IN std_logic;
		RX_ACK : IN std_logic;          
		RX_Byte : OUT std_logic_vector(7 downto 0);
		RX_OBF : OUT std_logic
	 );
end RX;

architecture Behavioral of RX is

component clkdiv
    port (
        clk     : in std_logic;         -- input clock
        nreset  : in std_logic;         -- active-low asynchronous global reset
        --
        clkout  : out std_logic         -- output clock
    );
end component;



signal RX_clock: std_logic;
signal RX_buffer: std_logic_vector(9 downto 0);
signal count: integer;
signal states: std_logic_vector(1 downto 0);
begin
thebaud: clkdiv port map (clk, not reset, RX_clock);


Receiving:process(RX_clock,reset)
variable bitcount: integer range 0 to 10;
begin
if reset='1' then
RX_buffer<="ZZZZZZZZZZ";
states<="00";--waiting for the first start bit;
RX_BYTe<="00000000";

else
	if RX_clock'event and RX_clock='1' then
	
		case states is
			when "00" => --Waiting for start bit;
				
					
				
				if UART_RXD ='0'  then
					states<="01"; --- read the next bit;
					bitcount:=1;
					RX_buffer<="ZZZZZZZZZZ";
					RX_buffer(0)<='0';
					RX_OBF<='0';
				end if;
			when "01" => -- Reading nine bits
				
					RX_buffer(bitcount)<=UART_RXD;
					
					if bitcount<9 then
						bitcount:=bitcount+1;
						
					else
						if UART_RXD='1' then --stop bit
							RX_byte<=RX_buffer(8 downto 1);
							--states<="00";
							RX_OBF<='1';
						end if;
						states<="00";---checking
					end if;

			when others =>
				states<="00";
		end case;
count<=bitcount;			
	end if;

end if;

end process;
end Behavioral;

 

[std_match]

It is working fine, but when I send from PC to the FPGA board, I face sometimes a wrong bits, My code is as follows: but would somebody please tell me why sometimes the data i receive inside the board are incorrect?

You must oversample the UART_RXD input. As it is now, you have no control over the sampling point. Sometimes you will sample too close to the bit borders and there will be errors.
You should not initialize an internal signal to "ZZZZZZZZZZ". It may work, but you will confuse other people and the synthesis tools.
You will probably save logic by implementing RX_buffer as a shift register instead of addressing individual bits.
You should put a range on all integer signals.

I also suggest that you use a high frequency "system clock" as the clock input and create a "clock strobe" for the baudrate related stuff. Clock nets are expensive, clock strobes are cheap.