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ROM in xilinx

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sngpl

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Hi,

I am using a ROM Core generator in xilinx to use some set of values in my code using ,coe file. All codes are written here. Basically there are 1560 output values. I want to use initial 160 in data 0 ,other 160 in data 1 and so on till data 08. But ROM gives output all together, How can i use the ouptut values in the way i want.

Here is the data i want as output:

Code:
timescale 1ns / 1ps
module memory0(addr, data0, clk);
input clk;
input [8:0] addr;
output [7:0] data0;
reg [7:0] data0;
wire [8:0] addr;
wire clk;
always @(posedge clk)
begin
case (addr)
9'd0:data0 = 8'd34;
9'd1:data0 = 8'd34;
9'd2:data0 = 8'd34;
9'd3:data0 = 8'd34;
9'd4:data0 = 8'd34;
9'd5:data0 = 8'd34;
9'd6:data0 = 8'd34;
9'd7:data0 = 8'd34;
9'd8:data0 = 8'd34;
9'd9:data0 = 8'd34;
9'd10:data0 = 8'd34;
9'd11:data0 = 8'd34;
9'd12:data0 = 8'd34;
9'd13:data0 = 8'd34;
9'd14:data0 = 8'd34;
9'd15:data0 = 8'd34;
9'd16:data0 = 8'd34;
9'd17:data0 = 8'd34;
9'd18:data0 = 8'd34;
9'd19:data0 = 8'd34;
9'd20:data0 = 8'd36;
9'd21:data0 = 8'd36;
9'd22:data0 = 8'd36;
9'd23:data0 = 8'd36;
9'd24:data0 = 8'd36;
9'd25:data0 = 8'd36;
9'd26:data0 = 8'd36;
9'd27:data0 = 8'd36;
9'd28:data0 = 8'd36;
9'd29:data0 = 8'd36;
9'd30:data0 = 8'd36;
9'd31:data0 = 8'd36;
9'd32:data0 = 8'd36;
9'd33:data0 = 8'd36;
9'd34:data0 = 8'd36;
9'd35:data0 = 8'd36;
9'd36:data0 = 8'd36;
9'd37:data0 = 8'd36;
9'd38:data0 = 8'd36;
9'd39:data0 = 8'd36;
9'd40:data0 = 8'd31;
9'd41:data0 = 8'd31;
9'd42:data0 = 8'd31;
9'd43:data0 = 8'd31;
9'd44:data0 = 8'd31;
9'd45:data0 = 8'd31;
9'd46:data0 = 8'd31;
9'd47:data0 = 8'd31;
9'd48:data0 = 8'd31;
9'd49:data0 = 8'd31;
9'd50:data0 = 8'd31;
9'd51:data0 = 8'd31;
9'd52:data0 = 8'd31;
9'd53:data0 = 8'd31;
9'd54:data0 = 8'd31;
9'd55:data0 = 8'd31;
9'd56:data0 = 8'd31;
9'd57:data0 = 8'd31;
9'd58:data0 = 8'd31;
9'd59:data0 = 8'd31;
9'd60:data0 = 8'd19;
9'd61:data0 = 8'd19;
9'd62:data0 = 8'd19;
9'd63:data0 = 8'd19;
9'd64:data0 = 8'd19;
9'd65:data0 = 8'd19;
9'd66:data0 = 8'd19;
9'd67:data0 = 8'd19;
9'd68:data0 = 8'd19;
9'd69:data0 = 8'd19;
9'd70:data0 = 8'd19;
9'd71:data0 = 8'd19;
9'd72:data0 = 8'd19;
9'd73:data0 = 8'd19;
9'd74:data0 = 8'd19;
9'd75:data0 = 8'd19;
9'd76:data0 = 8'd19;
9'd77:data0 = 8'd19;
9'd78:data0 = 8'd19;
9'd79:data0 = 8'd19;
9'd80:data0 = 8'd12;
9'd81:data0 = 8'd12;
9'd82:data0 = 8'd12;
9'd83:data0 = 8'd12;
9'd84:data0 = 8'd12;
9'd85:data0 = 8'd12;
9'd86:data0 = 8'd12;
9'd87:data0 = 8'd12;
9'd88:data0 = 8'd12;
9'd89:data0 = 8'd12;
9'd90:data0 = 8'd12;
9'd91:data0 = 8'd12;
9'd92:data0 = 8'd12;
9'd93:data0 = 8'd12;
9'd94:data0 = 8'd12;
9'd95:data0 = 8'd12;
9'd96:data0 = 8'd12;
9'd97:data0 = 8'd12;
9'd98:data0 = 8'd12;
9'd99:data0 = 8'd12;
9'd100:data0 = 8'd12;
9'd101:data0 = 8'd12;
9'd102:data0 = 8'd12;
9'd103:data0 = 8'd12;
9'd104:data0 = 8'd12;
9'd105:data0 = 8'd12;
9'd106:data0 = 8'd12;
9'd107:data0 = 8'd12;
9'd108:data0 = 8'd12;
9'd109:data0 = 8'd12;
9'd110:data0 = 8'd12;
9'd111:data0 = 8'd12;
9'd112:data0 = 8'd12;
9'd113:data0 = 8'd12;
9'd114:data0 = 8'd12;
9'd115:data0 = 8'd12;
9'd116:data0 = 8'd12;
9'd117:data0 = 8'd12;
9'd118:data0 = 8'd12;
9'd119:data0 = 8'd12;
9'd120:data0 = 8'd12;
9'd121:data0 = 8'd12;
9'd122:data0 = 8'd12;
9'd123:data0 = 8'd12;
9'd124:data0 = 8'd12;
9'd125:data0 = 8'd12;
9'd126:data0 = 8'd12;
9'd127:data0 = 8'd12;
9'd128:data0 = 8'd12;
9'd129:data0 = 8'd12;
9'd130:data0 = 8'd12;
9'd131:data0 = 8'd12;
9'd132:data0 = 8'd12;
9'd133:data0 = 8'd12;
9'd134:data0 = 8'd12;
9'd135:data0 = 8'd12;
9'd136:data0 = 8'd12;
9'd137:data0 = 8'd12;
9'd138:data0 = 8'd12;
9'd139:data0 = 8'd12;
9'd140:data0 = 8'd12;
9'd141:data0 = 8'd12;
9'd142:data0 = 8'd12;
9'd143:data0 = 8'd12;
9'd144:data0 = 8'd12;
9'd145:data0 = 8'd12;
9'd146:data0 = 8'd12;
9'd147:data0 = 8'd12;
9'd148:data0 = 8'd12;
9'd149:data0 = 8'd12;
9'd150:data0 = 8'd12;
9'd151:data0 = 8'd12;
9'd152:data0 = 8'd12;
9'd153:data0 = 8'd12;
9'd154:data0 = 8'd12;
9'd155:data0 = 8'd12;
9'd156:data0 = 8'd12;
9'd157:data0 = 8'd12;
9'd158:data0 = 8'd12;
9'd159:data0 = 8'd12;
default: data0 = 8'd0;endcase
end
endmodule
module memory1(addr, data1, clk);
input clk;
input [8:0] addr;
output [7:0] data1;
reg [7:0] data1;
wire [8:0] addr;
wire clk;
always @(posedge clk)
begin
case (addr)
9'd160:data1 = 8'd31;
9'd161:data1 = 8'd31;
9'd162:data1 = 8'd31;
9'd163:data1 = 8'd31;
9'd164:data1 = 8'd31;
9'd165:data1 = 8'd31;
9'd166:data1 = 8'd31;
9'd167:data1 = 8'd31;
9'd168:data1 = 8'd31;
9'd169:data1 = 8'd31;
9'd170:data1 = 8'd31;
9'd171:data1 = 8'd31;
9'd172:data1 = 8'd31;
9'd173:data1 = 8'd31;
9'd174:data1 = 8'd31;
9'd175:data1 = 8'd31;
9'd176:data1 = 8'd31;
9'd177:data1 = 8'd31;
.....
......
.....
9'd61:data7 = 8'd34;
9'd62:data7 = 8'd34;
9'd63:data7 = 8'd34;
9'd64:data7 = 8'd34;
9'd65:data7 = 8'd34;
9'd66:data7 = 8'd34;
9'd67:data7 = 8'd34;
9'd68:data7 = 8'd34;
9'd69:data7 = 8'd34;
9'd70:data7 = 8'd34;
9'd71:data7 = 8'd34;
9'd72:data7 = 8'd34;
9'd73:data7 = 8'd34;
9'd74:data7 = 8'd34;
9'd75:data7 = 8'd34;
9'd76:data7 = 8'd34;
9'd77:data7 = 8'd34;
9'd78:data7 = 8'd34;
9'd79:data7 = 8'd34;
default: data7 = 8'd0;endcase
end
endmodule

and here is .coe file I made :

Code:
; Sample initialization file for a
; 8-bit wide by 160 deep RAM
memory_initialization_radix = 16;
memory_initialization_vector =
34,34,34,34,34,34,34,34,34,34,34,34,34,34,34,34,34,34,34,34,36,36,36,36,36,36,36,36,36,36,36,36,36,36,36,36,36,36,36,36,31,

31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,12,12,

12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,

12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,31,31,31,31,

31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,33,33,33,33,33,33,33,33,33,33,33,33,33,33,33,33,33,33,33,33,28,28,28,28,28,

28,28,28,28,28,28,28,28,28,28,28,28,28,28,28,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,13,13,13,13,13,13,

13,13,13,13,13,13,13,13,13,13,13,13,13,13,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,

15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,28,28,28,28,28,28,28,28,

28,28,28,28,28,28,28,28,28,28,28,28,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,25,25,25,25,25,25,25,25,25,

25,25,25,25,25,25,25,25,25,25,25,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,14,14,14,14,14,14,14,14,14,14,

14,14,14,14,14,14,14,14,14,14,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,19,19,19,19,19,19,19,19,19,19,19,

19,19,19,19,19,19,19,19,19,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,24,24,24,24,24,24,24,24,24,24,24,24,

24,24,24,24,24,24,24,24,26,26,26,26,26,26,26,26,26,26,26,26,26,26,26,26,26,26,26,26,23,23,23,23,23,23,23,23,23,23,23,23,23,

23,23,23,23,23,23,23,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,15,15,15,15,15,15,15,15,15,15,15,15,15,15,

15,15,15,15,15,15,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,

22,22,22,22,22,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,

21,21,21,21,22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,

20,20,20,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,

16,16,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,26,26,26,26,26,26,26,26,26,26,26,26,26,26,26,26,26,26,26,

26,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,

19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,14,

14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,25,25,

25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,28,28,28,

28,28,28,28,28,28,28,28,28,28,28,28,28,28,28,28,28,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,

15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,13,13,13,13,13,

13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,28,28,28,28,28,28,

28,28,28,28,28,28,28,28,28,28,28,28,28,28,33,33,33,33,33,33,33,33,33,33,33,33,33,33,33,33,33,33,33,33,31,31,31,31,31,31,31,

31,31,31,31,31,31,31,31,31,31,31,31,31,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,

12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,

12,12,12,12,12,12,12,12,12,12,12,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,31,31,31,31,31,31,31,31,31,31,

31,31,31,31,31,31,31,31,31,31,36,36,36,36,36,36,36,36,36,36,36,36,36,36,36,36,36,36,36,36,34,34,34,34,34,34,34,34,34,34,34,

34,34,34,34,34,34,34,34,34;


Now I want to use output in a way that there are 8 data arrays and I use the values from the lookup table in the followng fashion :

memory0 mem0(addr,data0,clk);
memory1 mem1(addr,data1,clk);
memory2 mem2(addr,data2,clk);
memory3 mem3(addr,data3,clk);
memory4 mem4(addr,data4,clk);
memory5 mem5(addr,data5,clk);
memory6 mem6(addr,data6,clk);
memory7 mem7(addr,data7,clk);
 

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