Relative phase compensation technique

[Maitry07]

Hello support team,

I am working on a high speed ADC + FPGA . High speed ADC is multi channel that can take CW tone RF input and convert it into decimated I,Q digital data through DDC technique. I am providing 40 MHz RF input to high speed ADC channel 1 and channel 2 with the same cable length through function generator. My FG's channel 1 phase is 9.058 deg while My FG's channel 2 phase is 0 deg. FYI: I have checked my input's phase difference in MSO and validate that it is 9.058 deg

My FPGA is capturing decimated digital I,Q data for both the channels simultanously and I am using CORDIC IP core to convert the I,Q to absolute phase for both channel 1 and channel 2.
now, I am using subtractor IP core to have a difference between absolute phase 1- absolute phase 2 to generate relative phase.

and when I am checking output of relative phase , it is approximately 15 deg instead of 9.058 deg. weather this variation is due to slight mismatch between both the front end channel of my high speed ADC?
FYI: I am using AFE7900 High speed ADC.

What need to be done in order to compensate this relative phase misatch? is it ok to subtract 6 deg from the final relative phase output or any other proven method you can suggest to compensate this relative phase mismatch?

Awaited your response. if you need any other details, do let me know.

 

[Maitry07]

Hello,
Is there any feedback on the above attached zip analysis?

 

[kaz1]

Hello,
Is there any feedback on the above attached zip analysis?

My last post was the feedback of your excel file

 

[Maitry07]

For DC and 3MHz, the phase and amplitude are different. You should get at least amplitude to be close enough.

So your test is not valid for its purpose.
For now, test 3MHz only and also ignore your other scaling calculations, you don't need them. Just look at I,Q as they are.
Avoid initial sections as tone goes through DDC filters (just delete them from vector).
Still you need to capture both channels at same time as the 3MHz cycles around?

Please check in excel. My amplitude is same only for both DDC = 0 Hz and DDC = 3 MHz and for both channel 1 and channel 2

For amplitude , sqrt (I^2+Q^2) need to be done and after doing that , both channels amplitude are same at DDC=0 and DDC =3 MHz

--- Updated Nov 29, 2024 ---

Please check below I,Q data. Amplitude are similar for both the channels .

channel A _ I data	channel A _ Q data	channel B _ I data	channel B _ Q data
21563​	-19040​	-20188​	20775​
21574​	-19013​	-20226​	20743​
21607​	-18998​	-20256​	20718​
21584​	-18966​	-20277​	20729​
21640​	-18936​	-20300​	20665​
21655​	-18916​	-20307​	20643​

​

​

​

​

 

[kaz1]

Please check in excel. My amplitude is same only for both DDC = 0 Hz and DDC = 3 MHz and for both channel 1 and channel 2

For amplitude , sqrt (I^2+Q^2) need to be done and after doing that , both channels amplitude are same at DDC=0 and DDC =3 MHz

--- Updated Nov 29, 2024 ---

Please check below I,Q data. Amplitude are similar for both the channels .

channel A _ I data	channel A _ Q data	channel B _ I data	channel B _ Q data
21563​	-19040​	-20188​	20775​
21574​	-19013​	-20226​	20743​
21607​	-18998​	-20256​	20718​
21584​	-18966​	-20277​	20729​
21640​	-18936​	-20300​	20665​
21655​	-18916​	-20307​	20643​

​

​

​

​

OK you checked that and it looks close enough, just ADC noise variation expected. Now the phase is different, sort it out.
Also check your I/Q are not swapped by mistake.

 

[Maitry07]

OK you checked that and it looks close enough, just ADC noise variation expected. Now the phase is different, sort it out.
Also check your I/Q are not swapped by mistake.

No I have rechecked. My I and Q are not swapped. the offset increases with respect to frequency. so there has be some mismatch in the front end chain of the high speed ADC PCB. Let me check that.

--- Updated Dec 2, 2024 ---

OK you checked that and it looks close enough, just ADC noise variation expected. Now the phase is different, sort it out.
Also check your I/Q are not swapped by mistake.

No I have rechecked. My I and Q are not swapped. the offset increases with respect to frequency.

--- Updated Dec 2, 2024 ---

OK you checked that and it looks close enough, just ADC noise variation expected. Now the phase is different, sort it out.
Also check your I/Q are not swapped by mistake.

No I have rechecked. My I and Q are not swapped. the offset increases with respect to frequency.

 

[Maitry07]

OK you checked that and it looks close enough, just ADC noise variation expected. Now the phase is different, sort it out.
Also check your I/Q are not swapped by mistake.

No I have rechecked. My I and Q are not swapped. the offset increases with respect to frequency.

No I have rechecked. My I and Q are not swapped. the offset increases with respect to frequency. so there has be some mismatch in the front end chain of the high speed ADC PCB. Let me check that.

--- Updated Dec 2, 2024 ---

No I have rechecked. My I and Q are not swapped. the offset increases with respect to frequency.

--- Updated Dec 2, 2024 ---

No I have rechecked. My I and Q are not swapped. the offset increases with respect to frequency.

Hello,

I have checked and found below observation in terms of Front end.

For channel 1 and channel 2, single to differential balun is used.

For channel 1 , Input is transfer through primary dot of balun. while secondary dot is interfaced with Channel 1_N ( neg polarity) and secondary is interfaced with Channel 1_P (pos polarity) .


For channel 2, Input is transfer through primary dot of balun. while secondary dot is interfaced with Channel 1_P( pos polarity) and secondary is interfaced with Channel 1_N (neg polarity) .

That means , there is a polarity inversion between channel 1 and channel 2 with respect to RF front end.

There is also lane polarity for channel 1 at JESD side( SERDES lane) . while for channel 2, there is no lane polarity at JESD side.(SERDES lane). Polarity inversion at SERDES lane will not impact the relative phase measurement.

Also, I have calculated total transmission line length from channel 1 input to high speed ADC diffential input as below.
channel 1: approx. = 779.67 mil and channel 2 approx: = 714.15 mil

Based on the above, could you please let me know the relative phase offset reason and how to mitigate it

--- Updated Dec 2, 2024 ---

Polarity inversion cannot affect the actual measurement and cannot add the offset. It just add extra 180 deg inversion.

--- Updated Dec 2, 2024 ---

Polarity inversion cannot affect the actual measurement and cannot add the offset. It just add extra 180 deg inversion.

 

[kaz1]

"Polarity inversion cannot affect the actual measurement and cannot add the offset. It just add extra 180 deg inversion."

That is 180 degrees phase difference. You either fix it or invert it back in your final samples.

 

[KlausST]

Hi

post#48 now.
Is there a progress in finding the problem .. or better say finding a solution?

I guess we never have seen a schematic. I dot understand why ...

I still can not find results and conclusions when both ADCs are fed with identical signal.
One can find out whether it is a constant time delay ... or a filter characteristc delay (analog or digital filter, wanted or not wanted filter).
(A constant time delay would cause twice the phase shift .. on twice the input frequency. Phase and frequency are proportional
A filter may cause 0..90° phase shift [per order] .. and will NOT be linearely proportional to frequency)

I just had time for a quick view through the (incomplete) datasheet.
* in post#1 you talk about "simultaneous sampling". How? The ADC datasheet does not mention "simultan*" at all. Maybe it is, maybe not...
* when searching the (incomplete) datasheet about "phase" ... then it often mentions "calibration". Did you do the ADC / chip calibration?
Do you have the full dataheet? Because the calibration is not explained in the incomplete datasheet?
* the datastream has some latency. It is given as "typical" values only. No MIN and no MAX specification! .. so: unknown.

Klaus

 

[Maitry07]

Hi

post#48 now.
Is there a progress in finding the problem .. or better say finding a solution?

I guess we never have seen a schematic. I dot understand why ...

I still can not find results and conclusions when both ADCs are fed with identical signal.
One can find out whether it is a constant time delay ... or a filter characteristc delay (analog or digital filter, wanted or not wanted filter).
(A constant time delay would cause twice the phase shift .. on twice the input frequency. Phase and frequency are proportional
A filter may cause 0..90° phase shift [per order] .. and will NOT be linearely proportional to frequency)

I just had time for a quick view through the (incomplete) datasheet.
* in post#1 you talk about "simultaneous sampling". How? The ADC datasheet does not mention "simultan*" at all. Maybe it is, maybe not...
* when searching the (incomplete) datasheet about "phase" ... then it often mentions "calibration". Did you do the ADC / chip calibration?
Do you have the full dataheet? Because the calibration is not explained in the incomplete datasheet?
* the datastream has some latency. It is given as "typical" values only. No MIN and no MAX specification! .. so: unknown.

Klaus

Yes, I do have the datasheet of high speed ADC. PFA

 

[Maitry07]

Hello support team,

Is there any feedback on the above given datasheet. Have you find any conclusion?