Regarding maximum input data rate calculation for AD5754R DAC

[Maitry07]

Hi,

I have AD5754R DAC in my hardware . The DAC has 4 channels. I have a requirement to use output range as unipolar 5 V. so my DAC settling time for 0 to 5 V is approximate 2 usec as per datasheet. As I need to use all 4 channels simultaneously. I need to use the LDAC function as well. My input to this DAC all 4 channels will be from FPGA. In FPGA, I am capturing I and Q data and measuring Amplitude using square root of (I^2+Q^2). My measured amplitude for all 4 channels are of FIX16_14 format. In short I am getting 4 simultaneous outputs in FIX16_14 format . currently my sample rate for these measured amplitude data ( FIX16_14) is 20.48 MSPS. now I wanted to interface my these 4 simultaneous data with DAC 5754R SDIN input. But my confusion is about the input data rate AD5754R can take. As AD5754R datasheet does not provide any direct information related to sample rate or input data rate. I wanted to know, how can I calculate the input datarate for the AD5754R and as my current sample rate is 20.48 MSPS. based on the possible maximum sample rate acceptable by AD5754R, I need to decimate the same.

And also I need to understand the required SCLK in order to utilize AD5754R at its maximum. Do I need to use SCLK as 20.48 MHz only in order to sync the operation?

request you to provide guidance for the same.

 

[KlausST]

Hi,

such informations one does not store in brain. Thus I´d need to read the datasheet.
It would be helpful if you provide a link to the datasheet directly at the manufacturer´s internet site.
Additionally you could provide a link to the internet page of the device, because there usually are additional informations, like Application notes, Design notes, ... and so on.

Klaus

 

[Maitry07]

Hello,
Ok sure. Below are the link of the device
AD5754R DAC : https://www.analog.com/en/products/ad5754r.html
Application note: https://www.analog.com/en/resources/app-notes/an-1243.html
Evaluation board user guide: https://www.analog.com/en/resources...ware/evaluation-boards-kits/eval-ad5754r.html

From the datasheet, we have finalized output range as unipolar 5 V. and we have evaluation board as well along with my custom hardware and working properly. AD5754R has SPI interfacing that can be used with FPGA.

Let me know, if you need any other additional information to provide guidance.

 

[KlausST]

Hi,

Interface:
so if you want to update 4 channels, needing 24 bits to be transmitted each, with a maximum serial clock frequency of 30MHz....
makes 96 bits / 30MHz = 3.2us
Plus a bit of overhead for the control signals. Especially SDAC and LDAC. Let´s say 4us should be no problem.

Analog section:
Now if you want the analog output to settle completely (low error), then you have the 10us specification.

For me:
... as an electronics designer for decades - it´s the wrong way.
I always first decide the requirements of my application .. then .... I look for a suitable DAC.
For example: I´m not buying a drilling machine ... and later ask what I can do with it.

Thus:
I would like to ask about the application requirements.
You say the input data rate is about 20MHz, then you want to square, average and square root the values. The "average" needs to be done in an previously defined window. What´s this definition?


Klaus