Regarding maximum input data rate calculation for AD5754R DAC

[Maitry07]

Hi,

I have AD5754R DAC in my hardware . The DAC has 4 channels. I have a requirement to use output range as unipolar 5 V. so my DAC settling time for 0 to 5 V is approximate 2 usec as per datasheet. As I need to use all 4 channels simultaneously. I need to use the LDAC function as well. My input to this DAC all 4 channels will be from FPGA. In FPGA, I am capturing I and Q data and measuring Amplitude using square root of (I^2+Q^2). My measured amplitude for all 4 channels are of FIX16_14 format. In short I am getting 4 simultaneous outputs in FIX16_14 format . currently my sample rate for these measured amplitude data ( FIX16_14) is 20.48 MSPS. now I wanted to interface my these 4 simultaneous data with DAC 5754R SDIN input. But my confusion is about the input data rate AD5754R can take. As AD5754R datasheet does not provide any direct information related to sample rate or input data rate. I wanted to know, how can I calculate the input datarate for the AD5754R and as my current sample rate is 20.48 MSPS. based on the possible maximum sample rate acceptable by AD5754R, I need to decimate the same.

And also I need to understand the required SCLK in order to utilize AD5754R at its maximum. Do I need to use SCLK as 20.48 MHz only in order to sync the operation?

request you to provide guidance for the same.

 

[KlausST]

Hi,

such informations one does not store in brain. Thus I´d need to read the datasheet.
It would be helpful if you provide a link to the datasheet directly at the manufacturer´s internet site.
Additionally you could provide a link to the internet page of the device, because there usually are additional informations, like Application notes, Design notes, ... and so on.

Klaus

 

[Maitry07]

Hello,
Ok sure. Below are the link of the device
AD5754R DAC : https://www.analog.com/en/products/ad5754r.html
Application note: https://www.analog.com/en/resources/app-notes/an-1243.html
Evaluation board user guide: https://www.analog.com/en/resources...ware/evaluation-boards-kits/eval-ad5754r.html

From the datasheet, we have finalized output range as unipolar 5 V. and we have evaluation board as well along with my custom hardware and working properly. AD5754R has SPI interfacing that can be used with FPGA.

Let me know, if you need any other additional information to provide guidance.

 

[KlausST]

Hi,

Interface:
so if you want to update 4 channels, needing 24 bits to be transmitted each, with a maximum serial clock frequency of 30MHz....
makes 96 bits / 30MHz = 3.2us
Plus a bit of overhead for the control signals. Especially SDAC and LDAC. Let´s say 4us should be no problem.

Analog section:
Now if you want the analog output to settle completely (low error), then you have the 10us specification.

For me:
... as an electronics designer for decades - it´s the wrong way.
I always first decide the requirements of my application .. then .... I look for a suitable DAC.
For example: I´m not buying a drilling machine ... and later ask what I can do with it.

Thus:
I would like to ask about the application requirements.
You say the input data rate is about 20MHz, then you want to square, average and square root the values. The "average" needs to be done in an previously defined window. What´s this definition?


Klaus

 

[Maitry07]

Hello,

Let me brief you in detail. My application is to measure the amplitude of RF input.
For that , I am having 4 channel direct sampling Texas instruments receiver that can take RF inputs from signal generator and convert it to decimated I and Q ( 61.44 MSPS) using direct digital conversion technique. The Texas instruments Direct sampling receiver generate I , Q samples ( 61.44 MSPS) and transfer the same to FPGA using JESD protocol.

Once FPGA captures continuous I ,Q samples for all 4 channels, further digital signal processing to decimate the data rate to 20.48 MSPS as well as sqrt ( I^2+Q^2) and moving averaging are being done on the I and Q samples to generate amplitude in fix16_14 format.

Now I have this DAC- 5754R through which I need to further transfer my measured amplitude and convert it into analog voltage range of 0-5 V. so what I need to understand is that what is the exact calculation in terms of DAC 5754R. and at which sample rate I should provide my measured amplitude at the input of AD5754R SDIN line for all 4 channels.

From seeing datasheet, I understand that at every 1 usec, AD5754R is able to update its individual channel . so after 4 usec, all 4 channels are being updated. so, should I provide 1 channel SDIN ( 24 bits data) with a rate of 250 KSPS? Kindly provide me the guidance that with this DAC , what can be the ideal data rate in order to utilize this DAC at its maximum limit in a practical scenario?

I hope, I have given a detailed brief regarding my requirement. If any other queries, I am happy to answer.

 

[FvM]

I believe KlausST has calculated everything in post #4. Don't understand what you mean with "1 channel SDIN ( 24 bits data) with a rate of 250 KSPS". All 4 channels are updated with a rate of 250 kSPS. The exact rate depends on the chosen decimation ratio. How about 256, resulting in 240 kSPS?

 

[KlausST]

My application is to measure the amplitude of RF input.

What does "measure" mean here?
Is it for a human to read a display that shows the value? Then you don´t need to provide more than 3 values per second, since eyes and brain can´t process with higher speed.

so, should I provide 1 channel SDIN ( 24 bits data) with a rate of 250 KSPS?

I´m not sure I understand the whole system....
But fro me
(4 x 24 bits) x 250 kSPS is correct.

****

what can be the ideal data rate

I personally would synchronize input data rate with output data rate. So I guess you can´t use 30.000MHz (SPI clock frequency) but something slightlely different.
I´m not a friend of going to the very limit of the specifications ..


Klaus

 

[Maitry07]

Hello,

The all 4 amplitude measurement is for the control system. and As my main output data rate is 20.48 MSPS currently. DAC input data rate I am planning to use at maximum . so what should be the suitable SCLK and suitable SDIN data rate for single channel?

 

[KlausST]

Hi,

As FvM already stated ... your question should already be answered... and already repeated.
Thus I wonder why you again ask. What exact information do you expect?

so what should be the suitable SCLK and suitable SDIN data rate for single channel?

You now want to use "single channel" only?
For single channel .. the data rate would go up to about 1000 kSPS.

Klaus

 

[Maitry07]

No, I mean If I use single channel then I can use 1000 KSPS but If I use all 4 channels , then I can use 250 KSPS. but what should I take SCLK in order to sync.

--- Updated Today at 7:43 AM ---

Thank you for providing answer. I am just clarifying the same
I got your point

 

[KlausST]

but what should I take SCLK in order to sync

Now you ask about SCLK frequency ... before you asked about datat rate.

But .. I guess I also have answered it already. And FvM further explained that it depends on your decimation ratio.

But we can´t tell you what decimation ratio you should use. (Still FvM gave a number). It´s your application, only you know the application details.
The upper limit of 30MHz is given by the DAC datasheet.
Now it depends on you
* how much margin you want
* what decimation ratio you want
* and what deciamation ratio is possible

Klaus