Re: Problems with DesignCompiler/PrimeTime Flow

[Thawra-Kadeed]

Re: Problems with DesignCompiler/PrimeTime Flow

Actualluy the error is in the verilog cell library file:

# ** Error: /tools/synopsys_asic/cell_libs/UMC/65/verilog/uk65lscllmvbbh_sdf21.v(35589): $hold( posedge CK:2 ns, negedge D:2 ns, 1 ns );
# Time: 2 ns Iteration: 6 Instance: /testbench/top_level/sub_level_instance

I am doing just gate_level simulation directly with the output netlist from DC and when I am loading sdf file, I put in the region part: /tb/top_level which decreases this problem but I still have it.

 

[lengkeng]

Re: Problems with DesignCompiler/PrimeTime Flow

Hi,

I think you setup the SDF file error, you can try one of the following ways in turn:
1. Only read the netlist (not read the SDF) file, and make the simulation ==> any error?
2. Modify the SDF file (only include delay of one 1 cell), and make simulation ==> any error?
3. Check the region part (/tb/top_level) by change this to different value, and make simulation ==> any error?
4. ...

You can try different ways to debug the error by yourself before lauching the issue, ok?

Regards

 

[Thawra-Kadeed]

Re: Problems with DesignCompiler/PrimeTime Flow

Thanks for interesting, actually I tried all that you mentioned and other attempts before I launch the issue but it didn't work.

I think it's related more or less to the freq. itself which is going to go lower when we are using the gate level simulation.

Regards.

 

[slutarius]

Re: Problems with DesignCompiler/PrimeTime Flow

Actualluy the error is in the verilog cell library file:

# ** Error: /tools/synopsys_asic/cell_libs/UMC/65/verilog/uk65lscllmvbbh_sdf21.v(35589): $hold( posedge CK:2 ns, negedge D:2 ns, 1 ns );
# Time: 2 ns Iteration: 6 Instance: /testbench/top_level/sub_level_instance

I am doing just gate_level simulation directly with the output netlist from DC and when I am loading sdf file, I put in the region part: /tb/top_level which decreases this problem but I still have it.

Some points from your run:

1/ You use a netlist after synthesis with and SDF file. That is normaly meaningless.
The SDF of a pre-layout netlist are incorrect and no meaning.
The correct pair of netlist and SDF is the one taken from a post-layout database.

2/ That Error is from timing check task.
If you want the simulation to continue to run regardless the timing violation, you can disable the timing check.
Depends on you simulator, please google for how to disable it.

3/ Just my point, this constraint look strange to me becuase its round number in ns.
$hold( posedge CK:2 ns, negedge D:2 ns, 1 ns );