RAM data write and read

shared variable ram : memory_t;
	  begin
     process(clk)
     begin
     if(rising_edge(clk)) then -- Port A
      if(we_a = '1') then


		ram(addr_a) := data_a;

       -- Read-during-write on the same port returns NEW data
		 		case addr_a is
                when 0 => 
					 q_a <= "10000000";
                when 16 => 
					 q_a <= "10000000";
                when others => 
					 q_a <="00000000";
            end case;
       q_a <= data_a;
      else
       -- Read-during-write on the mixed port returns OLD data
		 		case addr_a is
                when 0 => 
					 q_a <= "10000000";
                when 16 => 
					 q_a <= "10000000";
                when others => 
					 q_a <="00000000";
            end case;
       q_a <= ram(addr_a);
      end if;
     end if;
     end process;