RAM data write and read

[Kosyas41]

Thanks for reply,but Im still dont understand this problem.My code looks like

shared variable ram : memory_t;
	  begin
     process(clk)
     begin
     if(rising_edge(clk)) then -- Port A
      if(we_a = '1') then


		ram(addr_a) := data_a;

       -- Read-during-write on the same port returns NEW data
		 		case addr_a is
                when 0 => 
					 q_a <= "10000000";
                when 16 => 
					 q_a <= "10000000";
                when others => 
					 q_a <="00000000";
            end case;
       q_a <= data_a;
      else
       -- Read-during-write on the mixed port returns OLD data
		 		case addr_a is
                when 0 => 
					 q_a <= "10000000";
                when 16 => 
					 q_a <= "10000000";
                when others => 
					 q_a <="00000000";
            end case;
       q_a <= ram(addr_a);
      end if;
     end if;
     end process;

and the same for another port. Compiler didnt show me any problems.but you told that I missing we_a or we_b.is it right now?

- - - Updated - - -

after when my project compiled.Im open Modelsim and got the following screens.I want to check how my project works,but as I can see nothing((

 

[dpaul]

Compiler didnt show me any problems.but you told that I missing we_a or we_b.is it right now?

Compiler won't complain on this issue.
You need to understand sensitivity lists. Google search: sensitivity list + VHDL
Else read the last part of this recent thread: https://www.edaboard.com/threads/356800/

after when my project compiled.Im open Modelsim and got the following screens.I want to check how my project works,but as I can see nothing

For functional verification of your design a test bench is required. The test bench provides stimulus to your design (commonly called DUT, design-under-test).

I don't know how you provided the clock signal. Basically the thumb rule is that you have to drive all your input top-level signals from the test bench. Since this is memory design, you might want to first wrote some data to addresses and then read them back for verification.