Questions about pll jitter

[leonwang]

Excuse me, how to simulate the jitter of a designed pll?
BTW, I use the cadence tools.

And how to decrease the jitter? Is there any optimizations?

Thanks a lot.

 

[sunking]

High order filter and good VCO can help improve the jitter.

 

[ablue]

higher gain may improve the performance, but the jitter of the input plays more if the input is not clean, you can refer to some papers of Gray or Lee

 

[moda]

You need to plot with your simulation the transfer phase gain ratio, (out/in phase gain) and now you can optimize your LPF for your need (that is minimize jitter)

I assume that your simulation is in the phase domain.

If your jitter still not good than consider noise in the VCO/POWER/LAYOUT.

 

[dumbfrog]

FFT + eye diagram

careful about => Layout, Layout, and Layout

 

[brmadhukar]

Hi,

Choice of the VCO is also needed. There are few VCO's that are better than others for particular application. The inductor plays a very big role.
If you are using the charge pump, you also need to take care of the reference frequency generator.
B R
M

 

[leonwang]

Thanks all of you.

1. I use the tools of cadence. Please tell me how to simulate the jitter with that.

If eye diagram, is the accuracy not satisfactory?
If FFT, please tell me how to carry with that.

2. I designed the VCO with ring osc. So is there some design skill to low the jitter
from VCO?

3. Until now, I did something to make the rise & fall time of signal from digital part
equal, current match, etc. What should I do else?

Thanks again.

 

[arsenal]

use spectre and add a vdc with a ac step
pos-divider needs to be retimed

 

[liluo]

You can analyze the phase noise of VCO.
Using a noiseless vco to analyze the phase noise floor caused by charge pump and dectector using spectre.

 

[xwcwc1234]

How to simulate the phase noise of VCO ? Using Hspice or matlab ? Anyone has some Matlab M-file or simulink file on this subject ?

 

[kkoko]

you can make phase noise and after that to transform in jitter

 

[xwcwc1234]

How to generate the phase noise and transform it to jiter ? Using Hspice or matlab ?

 

[huanchou]

If you want to simulate the PLL jitter, try to add the inductors in your power and ground to simulate the bounding wire then observe the control voltage variation.

 

[amarnath]

hello huanchou,that should give me the jitter probably caused by packaging etc.ok thats fine.suppose i have a 10mv variation in terms of the ripple in the control voltage of the vco.is it right in terms of a frequency specification of jitter that my jitter is =10e-3 * (gain of vco)/(2 *pi).then how to convert this to a time specification.

regards
amarnath

 

[nibo_mmx]

you can find information about jitter measurement from h**p://designers-guide.com.

Here is a link for jitter measurement.
h**p://

 

[amarnath]

i have read in most papers in IEEE that the pfd is not a major cource of jitter.but dont u think that if iam using a d flip flop architecture with minimal delay of say 12ps in order to greatly minimise my dead -zone.then the pulses generated by the pfd when in lock state will cause a ripple in the control voltage which leads to frequency jitter,although i can use a low pass filter to filter most of it,if i have a method of eliminating the ripple on the control voltage after lock ,will it not minimise my frequency jitter and also it should be minimising phase noise of the vco since phase noise will be affected by any ripple on the control voltage.please tell me if these things are correct.

regards
amarnath

 

[jerryhuang]

hi,amarnath
, pfd is mainly couse of what spe of pll?I also have a large ripple when my pll is locked,and the ripple is not decresed whit time pass,what is main reason of this jitter?should I use a low pass filter to decrese this ripple,the ripple got a timepieriod of 2us see foem the control votage of vco

 

[khouly]

what is ur refernce frequency
check the ripples it may be from references spurs

khouly

 

[amarnath]

hi,amarnath
, pfd is mainly couse of what spe of pll?I also have a large ripple when my pll is locked,and the ripple is not decresed whit time pass,what is main reason of this jitter?should I use a low pass filter to decrese this ripple,the ripple got a timepieriod of 2us see foem the control votage of vco

yes ur right to an extent.when u simulate ur pll without exposing it to the harsh on chip environment,then u may think this is the only reason.the ripple in the control can be minimised to a good extent by increasing the value of the capacitance,which is in series with ur resistance(iam talking about the filter used for charge pump type pll).but there is again a compromise when u do this because ur decreasing the loop bandwidth,which will affect your lock time.so a better thing to do is to use another kind of a pfd which will not output reset pulses even after lock.

regards
amarnath

 

[jerryhuang]

thanks,amarnath,my pll is a charge pump kind pll,my problem is when my pll is locked,see from the control votage of vco ,you will see a large and low frequence (about 120khz) ripple,and the votage ripple got a ampiltude as large as 2mv,so the output frequnce of vco has a large derivation as 200Khz from the carrier frequence.

Added after 4 minutes:

my vco gain about 50mhz/v,so the 2mv ripple is not aceptable ,but this low frequnce can not be descresed with a low pass filter ,becase this will need a low bandwith ,low gian filter ,can it be reality?
so i want to know what is the main reason of that kind ripple

Added after 14 minutes:

2 khouly

the pll is a fractional pll ,so my reference frequence is 20Mhz,the space is 300Khz,so is it a fractional spur?

Added after 6 minutes:

this is a ripple seee from contral votage of vco,not spur see from vco output frequence,so i think it is not the reference spur