Questions about DFT and scan chains on a chip

[satya_422]

Re: DFT question

How can the use of more scan chains reduces testing time very much.

yaa its good question :


data volume = no of channels* scanchain length * no of patterns

test cycles = scanchain length * no of patterns
test time = scanchain length * no of patterns * 1/frequency
scan chain length = no of scan cell/no scan chains

so if the length increases the time to shift increases
then the test volume increase.

then the test time increases

 

[carv_13]

Re: DFT question

so what would be an ideal number of flops per chain?

-Aravind

 

[satya_422]

Re: DFT question

so what would be an ideal number of flops per chain?

-Aravind

so for this we can go for the EDT
were we can have more scan chains and less no of scan channels
here the length of the scan chain is around 500 - 600
note: it depends on the flops present

 

[kiranks9]

Re: DFT question

How to decide the number of scan chain in a chip?
Ans: Depending the compactibility available numbet I/O pins on chip. In our design we used 8 scan chain. chip is supported to only 8 scan and scan out I/O pins at the top level

How to decide which flop should be in a specific scan chain?
When u doing the synthesis, u can use the multi clock option, the tool will put equal number of flops per scan scan.