Questions about DFT and scan chains on a chip

[sparc200]

DFT question

I have some questions about DFT,
How to decide the number of scan chain in a chip?
How to decide which flop should be in a specific scan chain?
Will this affect the placement and routing?
Thanks

 

[zhustudio]

DFT question

1. It depends on your ATE machine, how many scan chain can ATE support. And the more scan chain, the less test time. So it can save more cost in testing.

2. Generally, you should use dff in your design, do not use RS-flop and JK-flop. As far as I know, current DFT tools (DFT compiler and DFTAdvisor) does not support this kinds of flops. And the tools can optimize the scan chain, such as one chain in a module, and one chain in one clock domain. If you want to specify the flops by yourself, you can tell tools by scripting. But that is not the best optimization one.

3. Yeah, it will. Extra mux before normal flop will cause timing problem. And the scan routing is can effect routing significatently. But current routing tools have scan re-order. It re-orders the scan chain connection to avoid across in metal. So the ATPG will be done after the pnr stage, because of the final scan chains.

 

[archillios]

DFT question

and , what kind of ff should be used in DFT also depends on your vendor technology lib. some vendors provide LSSD，most vendors provide Multiplexed flip-flop.

 

[sparc200]

Re: DFT question

Thank you for your help. About the second question, I am sorry I did not make it clear, I am not asking what kind of flop to use, I am asking which flops should be grouped in one scan chain but not another.

 

[anjali]

Re: DFT question

1. the number of scan chains also depends on chip area. because more IO ports are required for more scan chains. chip area gets increased (small increase) even if we share the scan pins with the signal ports. but use of more scan chains reduces testing time very much.

2. i think tool doesn't give chance to specify which flop should be in a specific scan chain. in general scan chain will be stitched ( with a rough estimation on placement) in DFT analysis which is done after synthesis.

after placement, the scan chain will be rearranged based on placement.
if the tool gives that chance, optimization may get reduced, i feel.

3. placement & routing gets affected because the cells have more setup&hold periods.

 

[ldm]

Re: DFT question

Let's assume a multi-clock design with a lot of scan-chains. The clocks of the chains are not balanced.
The question is what methodology is usually used to connect between the chains in a top hierarchy?
Any links for related docs?

 

[anjali]

Re: DFT question

DFT is for testing of the strecture not for verification. so no matter of multiclock domains. all those comes in funtional mode. in test mode only test clk is used to shift the scan data through the scan chains.

 

[ldm]

Re: DFT question

In fact, today's digital chips usually have several (sometimes a lot of) scan chains, not only a single one with a single test clock.

What maximum number of FFs can you put in a single scan chain? 1K? 2K? And how many do you have in entier design? 50K? So, will you build a single scan chain consisting of 50K FF's or will you implement several scan chains? Are you able to build a balanced clock tree for all the 50K FFs? It seems there is another technique to insert a scan into multi-clock domain designs.

As far as I know, for a seperate clock domain, a functional clock might be replaced with a test one. But it's true for for a given domain only. Another clock domain will have another test clock, which is not balanced with the first one. So, test clocks balancing or another technique should be presented...

BTW, how to determeny how many FFs might connected in a single scan chain? Let's say you have 50K FF's in your design. So, how many chains should you build then?

 

[dongdong13]

Re: DFT question

how to deal with DFT and P&R

 

[z81203]

DFT question

number of scan chain & it's length are defined in module level by designer, and be redefined in chip level by integrator.

 

[anjali]

Re: DFT question

number of scan chains depends on ATE capability , chip area & in turn cost.

 

[ldm]

Re: DFT question

Could anyone provide some figures?

1) the longest scan chain he/she ever designed/seen
2) the max number of chains he/she ever designed/seen

just share your experience!

 

[sheikh145]

DFT question

in current proj for a particular module ,longest chain contained 80 flops and no of scan chains is 50

 

[dft_guy]

Re: DFT question

What the trade-offs are in scan chain length vs number of scan chains? It depends upon the design, the package, and the ATE, and the results affect test cost. It's really that simple.

Shorter scan chains = shorter test time = less test cost
Shorter scan chains also = more scan chains, given same amount of scannable flops
More scan chains = more package pins required (usually a constraint)
More scan chains also = more scan channels required on ATE (also usually constrained)

Which flops in which chains? Depends upon the design, clock domains, and your DFT tool. Most tools that do scan stitching do a good job of deciding that for you, once you define how many scan chains or the chain length (normally you wouldn't define both of those at the same time).

The scan implementation always has an effect on P&R. Sometimes scan stitching is not done until routing, so it is done with placement information and optimized that way. If stitching is done before P&R, the router may re-order the scan chain to reduce congestion. There's more than one way to do it.

John
for DFT talk/info go to:
DFT Digest
DFT Forum

 

[carv_13]

Re: DFT question

Do the tools have a limit to the number of flops that can be present in a scan chain?

-Aravind

 

[dft_guy]

Re: DFT question

No, there's no limit.

John
for DFT talk/info go to:
DFT Digest
DFT Forum

 

[vlsitechnology]

DFT question

If there is no limit then can we connect 50K flops to one scan chain ?

Added after 31 seconds:

and wts this scan stitching?

 

[dft_guy]

Re: DFT question

No problem at all. The downside is test application time - the longer your chains are, the longer it takes to shift data in. If you can, try to implement more parallel chains. But the scan stitching tool will happily implement one very long chain, and the ATPG tool will create patterns. It's just not a very good way to do it...

John
for DFT talk/info go to:
DFT Digest
DFT Forum

 

[vlsitechnology]

DFT question

How can the use of more scan chains reduces testing time very much.

 

[dft_guy]

DFT question

It's pretty much linear. For the same amount of flops, if you divide them in half (2 chains), and shift data in and out in parallel, it takes half the time to test them. Use 16 chains, and the test time is ~1/16 of the time it takes for one chain.

Example:
1 chain, 20k flops:
20k flops x 40ns clk_per x 1000 vectors = 800ms
2 chains 10k flops each:
10k flops x 40ns clk_per x 1000 vectors = 400ms

John