There is some truth in what mandrei said, but it is not quite corrent.
First of all, you have to make the distinction between the sample-and-hold circuit, and the processing afterwards. What happens during the sampling phase, is that a small capacitor is loaded. The bigger this capacitor is, the longer this phase takes. So as the input signal frequency rises, at a certain frequency the capacitor does not have the time any more to get fully charged during the sample-hold phase. The frequency where the digitized signal gets half that the size in the passband (3dB point) is what we call the analog bandwidth, or short bandwidth of the ADC. This bandwidth depends on the sample/hold circuit.
Now suppose we have a very fast sample/hold circuit. We can use this sampler, but digitize at much lower speed. E.G. we can digitize a 150MHz IF signal at 16MHz sampling clock, as long as the sample/hold circuit allows this. We call this subsampling. This is why your sampling clock is lower than the bandwidth. But note that every signal at 16MHz distance will be the same signal to the ADC. So this is why anti-aliasing filters are needed, so suppress these aliasing components.