Question about settling time of DAC

[gdhp]

hi jerryzhao lovseed and others

i am designing a 10-bit DAC. Its lowest power supply is 2.5V. And the output range

is 0-1.4V, LSB current is 36uA. In order to veryfy the INL<1LSB, i use the

cascode current source, the current source size is 12/2u. So the whole area of

current source array is too large to bear. But if decrease the size of unit current

size, when output is beyond the 1.0v, the cascode mosfet enters into linear. I

simulate the output impedance influence by dc sweep the output voltage, find the

output current is derease more than 1LSB when output reach 1.4V( is this

simulation method right?).

Another i try to use a single current source, when its size is 9/2, it also give much INL error.

Because my DAC area is limited, so the large size of current source mosfet is

impossible. But the INL<1lsb and DNL<0.5lsb requirement still exists.

So can you and others give me some suggestions about this problems? Is there

some method or paper deal with it?

Thanks a lot!

GDHP

 

[lovseed]

hi gdhp,
Some of my comments:
(1)power supply is 2.5v and max ouput is 1.4v. so there is only 1.1v left for current transistor/cascode transistor/switch.
Pay attention that the over-drive voltage of the current transistor can not be too low, otherwise you need much larger area to compensate the process mismatch.
Usually the over-drive voltage for current transistor is about 0.8-1v. It seems you voltage margain is not enough.
you need to eigher decrease the ouput range or increase the power supply.
What is your process node? 0.13?

(2)I think your simualtion for current variation is very creative.
(3)use single transistor will have bad DC and dynamic characteristic.

For item (1) you need refer to some ieee paper about the transistor area and mismatch calculation.

 

[jerryzhao]

I agree with lovseed.
The 0.5 LSB DNL maybe easy get. But The INL <1LSB it is diffcult.
For 2.5v supply the 1.4V output is large. U can use the different out, but that make a large die size.
Ur project is diffcult.
About die size, the good layout maybe save some size, but it's limited.
I am sorry, no good idea for you.

 

[gdhp]

thank you for your help!
So if the output is 0-1.4, so INL is large. So one method is fixed the output voltage by a opamp, so the non-linear by the channel length modulation is elimated.

BUt how the whole opamp feed-back structure make is still un-known.

Some suggestions?

gdhp

 

[lovseed]

thank you for your help!
So if the output is 0-1.4, so INL is large. So one method is fixed the output voltage by a opamp, so the non-linear by the channel length modulation is elimated.

BUt how the whole opamp feed-back structure make is still un-known.

Some suggestions?

gdhp

I have never seen any paper done this way.
if you fix the ouput voltage then you will fix the ouput of the DAC no matter that the input digital code is. This is not what you want ritht?

you may need to use differential ouput , that is to say the full-swing ouput is 0-0.7v for sigle end output.

 

[gdhp]

i think you misunderstand my meaning.
I fixed the dac output voltage with op, than the current output is translate into the voltage through the op. So the DAC is not directly output current.

Through fixed the output at the dac, the non-linear by L modulation is elemated.

is it clear?

Added after 20 minutes:

hi lovseed
another the diffiential output with 0-0.7v is also a good idea. But i must add a op to convert the diffiential to single output with 0-1.4v. Any idea about the diffiential op?

Is there any meterial about the idea?

 

[lovseed]

i think you misunderstand my meaning.
I fixed the dac output voltage with op, than the current output is translate into the voltage through the op. So the DAC is not directly output current.
Through fixed the output at the dac, the non-linear by L modulation is elemated.

is it clear?

Added after 20 minutes:

hi lovseed
another the diffiential output with 0-0.7v is also a good idea. But i must add a op to convert the diffiential to single output with 0-1.4v. Any idea about the diffiential op?

Is there any meterial about the idea?

Not quite understand how you will do that, anyway you can try and let us know your result.
For differntial to single end output, you need to read more books. (Razavi mentioned about this in cmos analog design book.) You need to pay attention to the differential input range of the opamp (0-1.4) and i donot know whether the convertion accuracy meet the DAC spec. Good luck.

And I have seen paper realize the differential ouput not in chip but on board. I can not provide more details since i have not done that.

 

[gdhp]

anywany thank you!

 

[zhjjwzz]

Thanx u,guys, I have learned a lot!