Question about settling time of DAC

[lovseed]

I am designing a 14-bit 50M current-steering DAC.

But I found it is hard to make the output stable (variation less than 61uV) in 20ns.
And the SFDR is only about 62dB for 23.4375M data and 50M sampling frequency.

How to make the output stable quickly, at least within 20ns?

Any good paper working on this?

 

[lovseed]

no experienced guys in this forum?

 

[rajanarender_suram]

what type of design style u r following (thermometer decoded/binary decoded)?

 

[lovseed]

segmented, 8 unary and 6 binary.

it seems that even the power supply is ideal , the settling time is about 25ns.

I need to keep the settling time to below 15ns.

 

[rajanarender_suram]

Try to reduce the glitch(which can be done by small modifications in the current-cells), because higher the glitch longer the settling time.

Added after 4 minutes:

I am designing a 14-bit 50M current-steering DAC.


And the SFDR is only about 62dB for 23.4375M data and 50M sampling frequency.


Any good paper working on this?

U r working with 50M clock for 23.4375M data which is near nyquit rate... its quite obvious that u get poor SFDR

 

[nathanee]

1. Try to use smaller switches size.
2. Tyr to use Nmos as current source.

 

[lovseed]

Now the situation is like this

If the power supply is almost ideal (with 1pH inductor on power supply path)
the result is very good with an SFDR=88dB.(The input ideal digital sinewave is 98dB SFDR).

However
with 1nH inductor on power supply path , SFDR＝61 dB
with 3nH inductor on power supply path, SFDR=54dB
with 5nH inductor on power supply path, SFDR=69dB.

I am using 400pf decoupling capacitor on digital power supply and 200pf decoupling capacitor on analog power supply.

It seems the noise on power supply affects the result much. In other words, the PSRR is not good. When 5nH added, the pk2pk noise on digital power is about 0.5v.

I am trying using larger decoupling caps.

Share your experience if you have ever designed a good DAC with good PSRR.

Added after 1 minutes:

Try to reduce the glitch(which can be done by small modifications in the current-cells), because higher the glitch longer the settling time.

Added after 4 minutes:

I am designing a 14-bit 50M current-steering DAC.


And the SFDR is only about 62dB for 23.4375M data and 50M sampling frequency.


Any good paper working on this?

U r working with 50M clock for 23.4375M data which is near nyquit rate... its quite obvious that u get poor SFDR

It is obvious that even with nyquist rate, you can still get good result if your design is good enough.

 

[zenisle]

for audio is only 20k bandwith

 

[mists]

in general, current DAC is used for video application

 

[jerryzhao]

Could you tell me the DAC's power supply and output swing?
The simulation result is right? Why the 5nH inductor's SFDR is better than others.
I think if you use the cascode, the PSRR will not very bad. And the noise is not main cause for bad SFDR( if noise very large is the main cause).
I think when you output swing change, the Vds of current MOS will small change. that will let DAC's INL bad. If you are not compensation that will lead a large harmonic distortion.
U should care it.

 

[lovseed]

Could you tell me the DAC's power supply and output swing?
The simulation result is right? Why the 5nH inductor's SFDR is better than others.
I think if you use the cascode, the PSRR will not very bad. And the noise is not main cause for bad SFDR( if noise very large is the main cause).
I think when you output swing change, the Vds of current MOS will small change. that will let DAC's INL bad. If you are not compensation that will lead a large harmonic distortion.
U should care it.

Sounds you are getting to my point!
I am also wondering why 5nH is better than 1nH/3nH. It is necessary to introduce how I get the result.

(1)simulation with input digital code for sine with 50*(15/32) MHz data frequency.
Sampling point is 512. which means the simualtion time is around 10.3us.
(2)Since the sampling clock is 50M (20ns), I am getting the 18ns result from each cycle to do FFT.Which means that i take the settling time to be 18ns( I think the final result should not worse than 18ns ).
(3)the full-scale single-end ouput is 1v.

Back to why 5nH is better than 1nH.
For both 5nH and 1nH , the ouput is not settled down to the desired value in 20ns. (seperate simulation shows that they need 50-80ns to settle down). So the 18ns result is actually a very random result, which makes 5nH happen to be better than 1nH.

But because 1pH result is very good, I am wondering whether the noise on digital/analog power which makes the output not settled.

I am using cascode and also used CFT cancellation circuit in switch.

I think you may be right, although the vds is relatively stable but it surely have some variation. But this will affect settling that much? And the compensation is to compensate ouput impedance or something else? Any paper on this?

Thanks

 

[gdhp]

"(2)Since the sampling clock is 50M (20ns), I am getting the 18ns result from each cycle to do FFT.Which means that i take the settling time to be 18ns( I think the final result should not worse than 18ns ). "
hi lovseed
when you do fft in hspice, how you can verify the point you get is the
settled point?
what is the meaning for "I am getting the 18ns result from each cycle to do FFT"?

 

[jerryzhao]

Hi lovseed:
Are your current cell always on? If the current cell always on, you put the output switch to out or out_. I think it will settle quickly. I think 18ns for settling time is enough. If DAC's output don't settle, I think u should check your current cell circuit and timing circuit.
Be care for the switch's timing and switch's size.
The size too small, it slow.but too large the clock feed-through is large.
Never shut down current in your current cell. otherwise it will not settle.
About compensation:
I add some current cell.I don't find some paper about it.
Only in my design, I add some current cell. When the output large I add a current cell to output especially the LSM block shift to MSB block.

 

[lovseed]

"(2)Since the sampling clock is 50M (20ns), I am getting the 18ns result from each cycle to do FFT.Which means that i take the settling time to be 18ns( I think the final result should not worse than 18ns ). "
hi lovseed
when you do fft in hspice, how you can verify the point you get is the
settled point?
what is the meaning for "I am getting the 18ns result from each cycle to do FFT"?

yeah, i do it in HSPICE. Just make sure the start time point, stop time point and number of points(512 as I used).

Added after 10 minutes:

Hi lovseed:
Are your current cell always on? If the current cell always on, you put the output switch to out or out_. I think it will settle quickly. I think 18ns for settling time is enough. If DAC's output don't settle, I think u should check your current cell circuit and timing circuit.
Be care for the switch's timing and switch's size.
The size too small, it slow.but too large the clock feed-through is large.
Never shut down current in your current cell. otherwise it will not settle.
About compensation:
I add some current cell.I don't find some paper about it.
Only in my design, I add some current cell. When the output large I add a current cell to output especially the LSM block shift to MSB block.

yeah, my current cells are always on. And the timing circuit are carefully designed with all control signals arriving almost the same time (within 500ps noise width). However the sso noise is very large with 5nH inductors and create large glitch in output. I think this sso glitch can not be moved if not with very very large decoupling. Any other good method?

I am wondering my cascode is working near border of saturation, which might make vds of current transistor varying much. ( I measured the pk2pk noise on the drain of current transistor is about 0.15v). I will check that way.

 

[jerryzhao]

1 When the power supply is ideal, make DA's settleing time < 15ns. I think u have done it.

2 Make the glitch as small as possible.

3 When simulate dirty power supply. please conect the two couple capacitor one 10uf another 0.1uf (PCB applaction connceted) then connect inductor with power.

4 If the digital power connect with analog power, Please use 1~2ohm's resistor connect D_power and A_power to main Power.

5 The main power, D_power(digital power), A_power all use couple capacitors.(the power on PCB connect like that)

Don't worry about it. I think everything will be ok.

 

[lovseed]

1 When the power supply is ideal, make DA's settleing time < 15ns. I think u have done it.

2 Make the glitch as small as possible.

3 When simulate dirty power supply. please conect the two couple capacitor one 10uf another 0.1uf (PCB applaction connceted) then connect inductor with power.

4 If the digital power connect with analog power, Please use 1~2ohm's resistor connect D_power and A_power to main Power.

5 The main power, D_power(digital power), A_power all use couple capacitors.(the power on PCB connect like that)

Don't worry about it. I think everything will be ok.

very good point!
I think what you mentioned emulate the real board/package parasitics but not only the inductors as what I have done.
My digital power is 1.8v and analog power is 3.3v. I am adding 400pf on-chip decoupling capacitors to 1.8v supply (this power is really noisy) and 200pf decoupling capacitors to 3.3v supply.
The decoupling caps are connected between vdd18/vss18 vdd33/vss33, and 5nH are connected between ideal power and vdd18, vdd33 , also between ideal ground and vss18, vss33. As simulation shows, the decoupling seems only make the noise on power/ground not so sharp, but still oscillate like part of sine wave. And it is fatal to the output, the output will also oscillate like that.

I donot know whether the big decoupling capacitors is implemented in chip or connected on board. If on-chip, it will cost so much area(maybe even larger than DAC itself). If it is on-board, it cheers me!

Also about the long-channel devices, i am using w/l=5.76um/44.4um current source transistor. The paper I referenced implemented the layout using snake liked channcel.(fold the channel length 3-4 times). I noticed you mentioned that you use transistors in series in another topic.


I have added more comments and questions on that. I think you should know much about that.

thanks a lot!

 

[jerryzhao]

1 Confirm current cell and cascode transistor always are saturated.
2 The next time you design current mirror, I don't think need use such accurate size of mos transistor.
3 The couple capacitor is on PC board, they are 10uF and 0.1uF, they are parallel.
4 When u give the DC step digital input, the most large glitch as small as posbile.
5 If you loading resistor is large. u can pallel a resistor in order to increase current, then decrease the settling time. (loading may be 75 ohm, you can parallel a resistor on PCB borad)
6 Ur W*L so large, so the die size is very large. I don't think it is good for mismatch.
7 Ur Engish is better than me.

 

[ADDA]

Hi,
1>Do you always add 0.1uf,10uf capacitors between power supply and ground when you simulate a circuit?

2>Does your DAC work well?

3>Can you share your DAC specification and the papers/thesis you referred ?

Best regards.

1 Confirm current cell and cascode transistor always are saturated.
2 The next time you design current mirror, I don't think need use such accurate size of mos transistor.
3 The couple capacitor is on PC board, they are 10uF and 0.1uF, they are parallel.
4 When u give the DC step digital input, the most large glitch as small as posbile.
5 If you loading resistor is large. u can pallel a resistor in order to increase current, then decrease the settling time. (loading may be 75 ohm, you can parallel a resistor on PCB borad)
6 Ur W*L so large, so the die size is very large. I don't think it is good for mismatch.
7 Ur Engish is better than me.

 

[lovseed]

Latest update:

If decoupling is big enough (say 1uf) The result is very good.(SFDR 89dB)

 

[jerryzhao]

1 I never design such high resulation DAC. I designed 8Bit 250M DAC. It work well.
2 I never add 0.1u and 10u capacitor when I do simulation, but I add those capacitor on PC board.
3 My DAC is graphic application I don't care the SFDR, So I never simulate the SFDR.
4 I desgned DAC is not the new design, It's redesign the old DAC.
5 I think the Timing and output inpedance is important.
6 All my pionts only for your information.

U can reference : Mismatch and Dynamic Modeling of Current Sources in Current-Steering CMOS D/A Converters: An Extended Design Procedure.
IEEE transaction on circuits and systems-I: Regular papers. VOL.51, NO.1, January 2004