Question about PA and applying maximum power level

[vfone]

Re: Question about PA

The control voltage (collector or bias) is driving only stage 2 and 3. First stage shall remain in the linear region. Some manufacturers drive also the first stage (just a little, if they can keep constant S11 vs Vcntrl).
In collector control, even at 10dBm and low supply voltage the PA is nearly saturation (due to low Vce)

 

[mckinson]

Re: Question about PA

I foud the PAE & POWER is related to the match for PA output ,
Do you think which the match is better ?

 

[mckinson]

Re: Question about PA

I am sorry just the one match is :0.5pF +3.3nH +0.5pF

 

[springf2000]

Re: Question about PA

i think the most important is the IMD figure of merit that y wanted! the more gain,the worse of this figure of merit! so y cannot judge what is the better match,that is decided by your application!

 

[vfone]

Re: Question about PA

Usually is a compromise between best efficiency match and best output power match.
In GSM (this is the application that we are talking about) because the PA input power is constant, the IM is not so important. Instead of best power match is preferred best efficiency match, to increase talk-time. This is the reason that mostly of mobiles on the market have the maximum output power with ~0.5dB less from nominal.

 

[mckinson]

Question about PA

Thanks for all the replys .
Yes ,the best efficiency can improve the call time .But the PAE is also related to the saturation for PA ,if the point of the maximum PAE is not correspond to the maximue output power ,so I think the PA is in the depth saturation situation when the maximum output power .Maybe some performance just Vfone say the switching transient ,harmonic ...get worse .

 

[chihhao]

Re: Question about PA

Some of transceiver output about 6~10 dBm power to PA module input.
I don't understand that when we set mobile phone output power level to minimum
power level such like DCS PCL15(0dBm) ,but the input power of PA is larger than
0dBm eg,.6dBm. What's the operation of PA in this situation ?
Thanks.

 

[Wilson_yu_chen]

Re: Question about PA

When PA is working on lowest PCL, 2nd and 3rd stages are basically no effect on gain which means you can take them as passive matching with loss,only 1st stage maintain linear region working mode. Transient and harmonic, even TX in RX band noise may increase if PA work on deep saturation or max power contour region. More hard hurdle of working on PA would be, from my points, would be optimization of power flatness at max PCL for PA front-end to the point before antenna connector. Usually layout parasitic effects on frequency response of front-end loss would make PA output match tweaking very hard by limited unchangable
factor of component placement, and even layer definition. If antenna connector located at the opposite side of PCB layer from PA/ASM, Via hole model could be magic to the solution of power flatness over frequenies.

Vfone, have you ever met similiar sight of me regarding to power flatness?

Best Regard,

 

[cygnet]

Re: Question about PA

the higher gain, the worse noise!
be careful

it is right.

 

[mckinson]

Question about PA

Hi ,Wilson how to judge a PA is working in saturation state ?
You mention the flatnesss , I think the loss from PA output to antenna connector is very important .If the VSWR of PA output is not flat ,I think the output power maybe not flat .Do you agree with me ?
Best regards !

 

[Wilson_yu_chen]

Re: Question about PA

When you get PA power output increase to the point where amount of current increase get lower than current data of previous power level by stepping up power ramp voltage, that point should be exactly deep saturation and no mention of maximum power PA can reach.

Yes, So sometime you may get really confused things that every stage with flat frequency response (TRSW, coupler, matching traces), but just STILL failed in power flatness !! Only thing I can say, we have to check combination cascade response rather than individual stages of match or component characteristic).
BUT in the end, EVERYthing counts on what PA sees for loading, we need some systematic rule to debug power flatness problem.

Thanks !

 

[chihhao]

Re: Question about PA

Wilson~
Regarding your post
"If antenna connector located at the opposite side of PCB layer from PA/ASM, Via hole model could be magic to the solution of power flatness over frequenies."

Could you explain it more detail ? Thanks.