Question about current source and improving area

[ilter]

current source question

Dear all,
My current source is w/L=64/20.How do I layout to improve area?
And if my current source is W/L=1/20 but they have 64.
Which one is good(64/20 or 1/20*64)?
If 1/20*64, how do I layout to improve area?
Thanks.

 

[fragment]

Re: current source question

Depends on structure of your current source.
But 64/20 transistors have less variation drain current than 1/20*64 ones.
And 64/20 consumes less area.

 

[ilter]

Re: current source question

If I use virtuso or laker, how do I do improve my area?
Because my W/L=1/20 current have 64 , it will be accurate.
Please tell me how to layout. Thanks.

 

[prabhu_psg]

Re: current source question

Hi

I beleive total capacitance reduces by using parallel transistor by factor of N.I have seen some layout for matching (centroid ,interdigitized ). but not sure aout the performance

Prabhu

 

[jiangwp]

Re: current source question

I think 1/20*64 is better than 64/20 in the theory.

But , generally, the scaling factor is less than 5. you have the factor of 64.

From the accuracy, 1/20*64 and 64/20 will not be improved more by careful layout aspect.

If you want to get a good current mirror, i think the reference shoud be incresed although the power disspation is incresed.

 

[tsanlee]

current source question

I think the 60/20 is better than other one.
The matching is dependend on W*L.
You can reference some paper JSSC 2001~2002
(Sorry I forget the real date)

I have one problem ,why do you decide the W/L (60/20 or 1/20 M=60) ,it need much area.

 

[ilter]

Re: current source question

I think the 60/20 is better than other one.
The matching is dependend on W*L.
You can reference some paper JSSC 2001~2002
(Sorry I forget the real date)

I have one problem ,why do you decide the W/L (60/20 or 1/20 M=60) ,it need much area.

I need current matrix.
I use mismatch parameter and current equation.
I will find W and L.
I have a equation.
If W/L=1/20, the factor is 64.
How do I do about layout to minimize layout area?
Thanks.

 

[tsanlee]

Re: current source question

My Suggestion is attach file:

 

[ilter]

Re: current source question

My Suggestion is attach file:

Dear tsanlee,
Can you tell me about W=? and L=? in your picture.And what size of just a transistor?( W/L=?).Can you tell me detail? Thanks.
My W=1u and L=20u

 

[ilter]

Re: current source question

For example, My current source is pmos.
It't W=1u and L=20u.Total cells number are 32.
I have another question.
Below picture, which one is good?upper or lower?
Thanks.

 

[tsanlee]

Re: current source question

I am Sorry, I made a mistake about length and width of PMOS .

I modify it linke attach file

In your layout ,I think the top figure is better than other one.
the effect of VGS is more than VGD in current mirror circuit.

 

[noiseless]

Re: current source question

There is no absolute which one is better. In the analog design, the most important thing is matching. This matching is refered to match with other transistors. So for the single transistor, there is no meaning which one is better. You need to think about what is the size of other transistors, using common central or interdigitate?
hope this helps