Pure CMOS bandgap reference voltage circuit

[slaphappybone]

cmos bandgap reference

Anyone have any recommendations as to what kind of readings is available in regards to the topic above? I need to design a purely CMOS bandgap reference voltage circuit and I do not know what kind of readings are suitable.

Thanks..

 

[SkyHigh]

pure cmos bandgap reference

I presume "pure" means basic or general CMOS bandgap reference voltage circuit.

Below are some popularly used textbooks used by practising analog IC designers and post/undergraduate students:

1. Johns, Martin, "Analog integrated circuit design"
2. Gray, Meyer, Hurst, Lewis, "Analysis and design of analog ICs"
3. Allen, Holberg, "CMOS analog circuit design"
4. Razavi, "Design of analog CMOS integrated circuits"

You can find bandgap reference design in there.

 

[sunking]

cmos bandgap reference circuit

 

[slaphappybone]

bandgap cmos voltage

I would like to design the circuit entirely with CMOS transistors only. Most of the time, the papers and journals use both BJT and CMOS..

 

[snoop835]

parasitic bjt used in bandgap reference

Maybe you get the concept slightly wrong. In conventional CMOS bandgap reference, you can realize a bipolar transistor, that is using the parasitic bipolar devices inherent in CMOS Technology. This is the common method in nowadays process.

You can refer to 'Voltage References' by A. Rincon Mora. It s a good reference to design bandgap references.

Here are some journals that might helps.

 

[nEuron]

gray meyer cmos bandgap

U can realize a purely CMOS bandgap reference by using MOSFET working in subthreshold region, which having similar characteristic as BJT. The drawback is that a bigger area is needed as compared to bandgap realize in BJT.

Besides than above mentioned method, in fact u can refer to the attached paper by K.N Leung.

 

[electronrancher]

i wouldn't use mos in subthreshold if i were you - the matching is quite bad. use two diodes of different size - for example, the p-drain to n-well diode is good in an n-well process. just draw a square of drain (with contacts), then copy and paste this structure 8 times in a ring around your first diode. now you have a 1:8 diode you can use for a delta vbe.

|--------| <- N-well
| B B B |
| B A B | <- Multiple areas of P+
| B B B |
|--------|


one note - it's better to make a repeating structure than to make one little diode and one big one - you want the same oxide cuts, the same contact-FOX distance, etc. so they will match.

now that you have a delta-vbe, the rest (an amplifier) should be easy..

 

[nEuron]

This is a good idea. But do we need to model it before it can be used for simulation? in my process that i m using now, i can't find such model in my library.

 

[Fom]

Hi, electronrancher!
Do you have any information how bad the matching for subthreshold region in comparision with normal operation

 

[electronrancher]

I have no matching criterion of subthreshold, but matching of a mosfet follows square root of mosfet size and Vds. I expect the matching trend for the most part follows normal mosfet matching criteria (because of the physical processes that cause mismatch - they are unrelated to region of operation. in essence, mos cannot compete with the matching of a diffusion, which in a local area is very uniform.

as for a model - i'm sorry, if your process does not provide it, you must extract it yourself. i have extracted the P+ to N-well diode in two of our cmos processes (different fabs) from 0.1 to 100uA at 0, 25 and 85C. this model may seem crude, but it worked well enough to compete with the higher option process that does provide vertical npn (and had real models).

really, the trick is to make the diodes big enough (5umx5um or so) that the variation in this tiny area has little dependence on oxide etch, which varies a great deal from lot to lot. very small diodes will have proportionally rougher edges, which shows up as a large variation in diode area, and therefore a large variation in vbe, and necessitates a larger trim range. in fact, a good rule of thumb is to make the width 5x or 10x the junction depth so the pn junction has more flat bottom than rounded edge.

 

[Fom]

I found a paper about transistor mismatch in subthreshold region.

Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits.

This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Jan. 2004
Volume: 39, Issue: 1

We further show through experimental results that the Vth mismatch of paired transistors working in the subthreshold regime can be worse by a factor of two as compared to transistors working in the saturation or linear regions.

 

[wjx197733]

nEuron:but the parameter such as w/l is ?

 

[nEuron]

Hi wjx197733,

in order to operate the MOS in subthreshold, the aspect ratio has to be large, which will occupy a large area. it is depends on how you choose ur VGS, of course VGS must be less than VTH.

 

[wjxcom]

Hi nEuron: The MOS is in msubthreshold? and VGS is less than Vth? why?

I think But why the slew rate is related to bandwidth is supply voltage to the circuit, so MOS in bandgap circuit should be in saturate.

 

[tony_wu_ad]

yeah, so many document that i want

thanks!

Added after 3 minutes:

no points
can not download file

 

[xwcwc1234]

Design a bandgap refernce work in subthreshold is difficult for me in terms of relibility and stability. Anyone has experience on this matter is welcome to explain .

 

[starcoming]

you can also use substarte parastic pnps when use pure CMOS technology.

 

[atghiaee]

Anyone have any recommendations as to what kind of readings is available in regards to the topic above? I need to design a purely CMOS bandgap reference voltage circuit and I do not know what kind of readings are suitable.

Thanks..

Hi You may refere to the Analog Integrated design books writen by Gray and Mayer or qriten by K. Marin or writen by B. Razavi.
Good luck...! A. Atghiaee