PTAT Circuit and stability (positive feedback)

[LvW]

Hi palmeiras,
I`ll try to answer your questions:

1) I cannot see how breaking the loop in this conditions (small output resistance + large input resistance), will mitigate the impact of breaking the loop, in terms of impedance. Do you have a suggestion for me to understand this rule?

This rule (low output resistance) is important only if you choose the "simple" way of simulating the loop gain (that means: without mirroring the load). Example: 1kohm output resistance is connected to a 1kohm load. Result: output voltage is different with/without load. If you break the loop at this point there is no current anymore flowing out of the output node, unless you connect a "mirror load" at this point. In most cases, however,this load is unknown and frequency dependent. Then, an exact mirror is not possible. If the output resitance is pretty low and/or the connected load (input of the next stage) is sufficient high you don`t need such a mirror - and the error is (hopefully) negligible.

2) You commented about circuits with amp. op. It is normal to break the loop at the output node. However, amplifiers often have high output resistance in order to increase the small signal gain. Am I correct or not?.

Really "often" ? What I call "operational amplifier" is a voltage amplifier with a high input and a low output resistance.
Of course, if this is not fulfilled, my arguments are not valid anymore.

For example, differential pair with cascade devices or a folded cascade amplifier, present transistors with high values of output resistance. When in these cases, the amp. op output resistance is high, why is it proper to break the loop there?

I think that such amplifiers with a current output are called OTA or transconductor or voltage-current transducer.
In such a case, most probably, the high resistance voltage input is the best point for breaking the loop. Or you must apply more sophisticated arrangements that are independent on such restrictions (Middlebrook,...)

3) When we are breaking a loop at some node, we always are changing the load conditions there. Am I correct or not?
So, the key point on your explanation is that "we should minimize the change of the impedance as much as we can". Did I get your message?

Yes, correct. Remember: Nothing in electronics is correct by 100%. Even each multimeter application changes the value to be measured.
Regards
LvW

 

[palmeiras]

Hi LvW,

Thank again for your comments. I got your explanation and I will continue studying this issue. Considering the BGR shown in figure 1, and with a diff. pair as error amplifier, I believe that the best point to break the loop is “node A”. Because it is a low output resistance (1/gm) connected to high input resistance, gate of the input pair). Am I right? :-D

Thanks,
we see each other in other EDA topics.

 

[LvW]

Hi palmeiras,

you have picked up a very specific case - an opamp with positive and negative feedback at the same time.
In such a case you must open both feedback loops - that means: disconnect both branches from the opamp output and inject the test signal BETWEEN node P and the opamp output. Then, the loop gain is V(P)/V(out).
Remark: This is a simplified version of the method as described by Middlebrook. This method preserves the operating point - and no load mirror is necessary because the opamp output resistance is low enough.

 

[palmeiras]

Hi LvW,

You are right... I did not choose a good example! :-D hehehe
Regarding the loop gain, do you mean “V(out)/V(p)? Once you are injecting a test voltage at node P, and measuring the output of amplifier.

I took a look in the Prof. MiddleBrook website and checked some of his slides. It seems to be a different approach compared with traditional electronic books. I had heard about Structured Analog Design before (Prof. M. Kayal – EPFL), however MiddleBrook´s has attracted my attention.
What books of this author have you read? Or have you study his DVD (Technical… etc)?!

 

[LvW]

Palmeiras,

at first, you are right - of course, the gain is V(out)/V(P).
Regarding the Middlebrook method: I really don`t remember when and how I came into contact with his method.
Did he write a book? But I can give you a rather good and interesting reference for this and some other methods for loop gain simulation::
Loop Gain Simulation - Frank Wiedmann

Regards

 

[palmeiras]

Lvw,
Thanks. I will take a look in the website you´ve suggested.
A list of publications of Prof. Middlebrook can be accessed in: Books, papers, CDs and DVDs - Resources. He has written some books, but I believe this subject (Feedback simulation) is specifically treated in the following journal:
Measurement of Loop Gain in Feedback Systems
Intl. J. of Electronics, 38, 485—512, Apr. 1975.
I will try to read it too.

Regards,

 

[palmeiras]

Hi LvW,

Thank for your reply in the topic: “phase margin measerument with HPICE)”;
Yes… I have understood your explanation. If possible, could you clarify the following doubt?
1) Regarding the positive feedback that you´ve mentioned. If the loop gain is less than one (as we discussed in this topic), the system is stable independently of the phase?
2) For you, does the setup measurement shown in figure 1 - in the open loop configuration – gives relevant data about the stability? I´m asking this because I have seen this setup many times, but it is strange for me, since there is no feedback.