PTAT Circuit and stability (positive feedback)

[palmeiras]

Hello guys,
Please, can someone help me with the following doubts about the traditional PTAT circuit?

(a) How does the positive feedback work in this circuit?
(b) How can I simulate the stability of this circuit using HSPICE?
(c) When the circuit presents a positive feedback, how can I ensure a stable operating point? Sedra Microelectronics book says that making K > 1.0 avoid instability. For me it is not clear. I know that making K higher than 1 we have Iout different than zero, but this does not explain the stability issue.

Thank you very much in advance,

Best regards,

 

[leo_o2]

I think this circuit will not have stability problem. One thing you need to take care is Vth mismatch in M1 and M2. Sometimes it will lead to zero current.

 

[palmeiras]

Thanks leo_02 for your reply. By the way, do you understand the positive feedback of this circuit and how to simulate the stability? If yes, could you explain?
Best regards,

 

[LvW]

pameiras, why do you expect "positive feedback" in the circuit?

 

[mastericke]

This is positive feedback, but remember, if its gain when positive is less than 1, it will also stable, because the signal will not been Amplified

 

[checkmate]

mastericke is right, you need a loop gain of less than 1.
The loop gain is given by
gm2/(gm1)(1+gm2*Rs)
As you can see, loop gain is guaranteed to be less than 1 in the stable state.
You can verify this in simulation by running a transient, making sure that you include a startup circuit to bring the circuit to its stable operating point, capture the DC operating point and run an AC analysis. Do remember you need to break the loop to get the loop gain.

In the transient startup phase, the positive feedback actually helps by bringing the current to the stable current level very fast, but too large a gain during this transient phase may actually result in overshoots which may be a headache depending on your application.

 

[palmeiras]

Hi checkmate, mastericke and LvW, thank you for all replies.

LvW,
For example, suppose that the voltage at the drain of M1 increases for some reason, this will increase the VGS voltage of M1 and M2, therefore increasing their currents. If Iout is increased, the current mirror forces Iref to increase too – resulting in a continuous increase. At least is the way that I think. Please, tell me if you disagree with the above example.

Checkmate,
1- Please, could you explain how you get this loop gain equation? Did you use the small signal model for all transistors or other easier way?
Regarding the start-up circuit, I have already designed it.
2- Where would you break the loop to simulate the AC behavior?
3- Do I break the loop and insert an AC source with “1” volt? After that, which node do I need to check?

Thanks very much and best regards.

 

[LvW]

Hi checkmate, mastericke and LvW, thank you for all replies.
LvW,
For example, suppose that the voltage at the drain of M1 increases for some reason, this will increase the VGS voltage of M1 and M2, therefore increasing their currents. If Iout is increased, the current mirror forces Iref to increase too – resulting in a continuous increase. At least is the way that I think. Please, tell me if you disagree with the above example.

Palmeiras, no sorry, I disagree with your explanation. You should take into consideration the factor K and the source resistor of M2. Both modify the transfer characteristic of M2 and make it more linear than the M1 characteristic.
This leads to a certain operating point where both curves meet each other.
Now, when for example the current Ids1 through M1 decreases slightly, the current Ids2 through M2 does NOT decrease accordingly (because of another linearized characteristic of M2). Instead, Ids2 remains larger than Ids1 (because of the factor K) and its value will be transferred via the mirror M3-M4 to M1 again. Thus, The Ids1 increase will be reduced to a smaller amount.
This is a typical effect of negative feedback.

One additional remark concerning stability:
The M3-M4 mirror always ensures Id1=Id2. However, due to different Ids-Vgs transfer characteristics of both transistors M1,M2 this identity is possible only in one single operational point (where both curves cross). This ensures stability.

---------- Post added at 15:36 ---------- Previous post was at 13:47 ----------

Here is another explanation, which - perhaps - is more clear:
If Ids1 increases due to some temperatur changes (first of all without touching Vgs1) , this increase is transferred via M3 and M4 to M2 leading to an increased votage drop across Rs. Thus Vgs2=Vgs1 is reduced with the consequence that Ids1 is decreased again. A typical negative feedback effect!.

 

[palmeiras]

Hi LvW,
I´m sorry for the delay to answer. Thanks for your reply.

1) You are right. I should take into account the factor K and the source resistor. However, I have not still understood your point. I cannot see how the increase in IDS1 can be transferred to M2 through M3 and M4. The diode connection in the current mirror is in M3, not in M4. Therefore, I think that any changes of current or voltage at the drain of M1, it only can be transferred to the current mirror through M2. Please, tell me if you agree now?

2) I think it is positive feedback because:
“ Any increase in the voltage at the drain of M1 (let´s say delta_V) would be transferred to the drain of M2, through the gate connection of M1 and M2. However, as M2 acts as “source amplifier” with source resistor, the gain of this configuration is always less than one. Consequently, this “delta_V” will be reduced, and transferred to the drain of M1, through the current mirror. I think the key point of this discussion is the gain lower than one, as explained by mastericke and checkmate.

3) Finally, I still need to understand how to find the loop gain equation proposed by checkmate.

Thanks and best regards,

 

[LvW]

Hi palmeiras,

I`ll try to explain my sight in detail:

1) You are right. I should take into account the factor K and the source resistor. However, I have not still understood your point. I cannot see how the increase in IDS1 can be transferred to M2 through M3 and M4. The diode connection in the current mirror is in M3, not in M4. Therefore, I think that any changes of current or voltage at the drain of M1, it only can be transferred to the current mirror through M2. Please, tell me if you agree now?

Start with an increase in Ids1 (for example due to temperature change). Because of Ids1=Ids4 and Ids4=Ids3 this change is transferred to Ids3, OK? Now, Ids3=Iout is also identical to Ids2. That means, Ids2 tends to increase as much as Ids1. However, due to RS1 an additional voltage is created across this resistor leading to a reduction in Vgs2=Vgs1. That means, the reduced Vgs1 voltage works against the initial Ids1 increase and, thus, can reduce this increase to a smaller value.
And this is a typical negative feedback effect (no positive feedback at all).

2) I think it is positive feedback because:
“ Any increase in the voltage at the drain of M1 (let´s say delta_V) would be transferred to the drain of M2, through the gate connection of M1 and M2. However, as M2 acts as “source amplifier” with source resistor, the gain of this configuration is always less than one. Consequently, this “delta_V” will be reduced, and transferred to the drain of M1, through the current mirror. I think the key point of this discussion is the gain lower than one, as explained by mastericke and checkmate.


The signal variable in the circuit is a current - not a voltage! Therefore, you have to start with a change in current (due to temperature variation or because an external current is drawn). By the way: What could be the reason for a sudden voltage change? More than that, M2 does not act as an amplifier with a gain less than one. This view is correct only if you consider an input voltage at the gate of M2 and an output voltage at the M2 drain. But - as mentioned above - we have no signal voltages in the circuit. It is the current which matters only.
(How can "a delta_V be transferred .... through a current mirror" as you write?)

3) Finally, I still need to understand how to find the loop gain equation proposed by checkmate.

Normally, we have to face voltages as variables and there are established methods for simulating the voltage loop gain.
Here we have currents and you must inject a test current into the Ids1 path and watch the reaction of the loop.
This seems to be a bit tricky and I have to think about it.
LvW

 

[LvW]

Hi palmeiras,
here some remarks regarding feedback in the circuit.
I think, we have to realize the purpose of the circuit: That is to provide a currrent that is (nearly) proportional to temperature.
Because of IC technology temperature changes not only in one single path but simultaneously in both branches, that means:
Both currents (Iref and Iout) change at the same time and in the same amount (due to the M3-M4 mirror).
In case K=1 and Rs=0 this would be problematic because it is not clear which mirror determines the equality of the currents (M3-M4 or M1-M2). This is ment when the term "stability" is mentioned - and this has nothing to do with feedback stability.
But with K>1 and a proper Rs value there is a fixed operating point (crossing point of different Vgs-Ids curves , see my former answer). Therefore, both currents Iref and Iout increase with temperature - but in a more or less linear manner due to Rs negative feedback (classical linearization effect of negative feedback).
And that`s the only feedback action in the circuitry. Derived from transistor basics, the loop gain of this local loop is LG=-g2*Rs.
(I repeat my former question: Why do you think there could be any positive feedback?).

LvW

 

[palmeiras]

Hi Lvw, thanks again for your contact.

1) When you wrote: “the resistor leading to a reduction in VGS2=VGS1”. Do you mean VGS2 minus VGS1, right? Because VGS1 is always different from VGS2, never equal.

2) I agree that the current is the main variable in the circuit. But I don’t agree completely with the exclusion of “delta_V analysis. Independently if the main variable is current or voltage, the physics is the same. For instance, the drain of transistor M1 can be affected by a “delta_V” coming from a noise coupling; and this circuit needs to respond properly for this spurious signal.

When I wrote “a delta_V be transferred …through a current mirror”, I mean that a delta_V at the drain of M1 will result in a “delta_I” in the drain of M2 – because the “amplifier” behavior, that consequently it will be transferred through the current mirror.

3) I agree with you, I will make a simulation injecting a “delta_I” in that node.

4) Answering your last question: I concluded the circuit has positive feedback because my analysis considering “a delta voltage” as variable input; what I thought to be correct. Nevertheless after your explanation, I´m a little bit confused :-D hehehehe

5) I agree with you regarding your last considerations about K=1 and RS=0. By the way, where do you break the loop to check the open-loop gain? How do you do this analysis using HSPICE?

Thanks very much for this good conversation.

A last thing: I tried to find some book that discuss this issue, and I only found it in Microelectronics - Sedra.... if you are curious, take a look in page 757, in the fifth edition. He only says that there is a "positive feedback", and does not give interesting answers.

 

[LvW]

Hi palmeiras,

here are some new outcomes from my side:

1) When you wrote: “the resistor leading to a reduction in VGS2=VGS1”. Do you mean VGS2 minus VGS1, right? Because VGS1 is always different from VGS2, never equal.


Sorry, this was a typo: Of course it must be Vgs1=Vgs2+Ids2*Rs=Vgo2 (referred to ground).

A last thing: I tried to find some book that discuss this issue, and I only found it in Microelectronics - Sedra.... if you are curious, take a look in page 757, in the fifth edition. He only says that there is a "positive feedback", and does not give interesting answers.

After this, I have reconsidered the problem - and I found that, indeed, you can define a loop gain within the circuit which turns out to be positiv. Although I wrote that the (main) signal variables are currents there are also voltages (gate connections) that contribute to the circuits behaviour.
Therefore, you can for example open the loop between gate 1 and gate 2. In order to restore the original operating point a corresponding dc voltage has to be applied to gate 2 - in series with a test signal voltage for measuring the loop gain.

I have done some simulations with a proper designed PTAT circuit containing only bipolar devices.
And the result wa a loop gain of +0.325.
I must confess, it`s the first time I have investigated such a PTAT circuit in detail - and I have learned something.
Regards to you
LvW

---------- Post added at 10:48 ---------- Previous post was at 10:32 ----------

As you probably know, a positive loop gain is not a problem and will not cause instabilities - as long as it remains below unity.
And in this context, the resistor Rs plays an important role.

 

[erikl]

I have done some simulations with a proper designed PTAT circuit containing only bipolar devices.
And the result wa a loop gain of +0.325.

I found 2 more publications which deal with this PTAT or a similar CTAT circuit, which might be of interest.

For the 1st one -- a (nearly) CTAT circuit -- the author Eric Vittoz also states a positive feedback for a similar loop (see the 2nd page of the foll. PDF). Even if this loop contains one more transistor (M2) I think it doesn't change the overall feedback consideration, as it works in a gate based configuration, hence IMHO causes no phase inversion between source and drain (Vs↗ ⇛ Vgs↘ ⇛ Ids↘ ⇛ Vd↗).
View attachment Resistor-less_constant-current_reference.pdf

Another paper also deals with the dynamic properties of the original PTAT circuit.
I got it a few years ago from the EDAboard forum, but don't remember where from, nor was its origin given: View attachment self-biased_micro-current-generator.pdf

 

[checkmate]

Hi checkmate, mastericke and LvW, thank you for all replies.
Checkmate,[/B]
1- Please, could you explain how you get this loop gain equation? Did you use the small signal model for all transistors or other easier way?
Regarding the start-up circuit, I have already designed it.
2- Where would you break the loop to simulate the AC behavior?
3- Do I break the loop and insert an AC source with “1” volt? After that, which node do I need to check?

Thanks very much and best regards.

1- The small signal model is used. The presence of the gm term already indicates that this is a small signal equation.
2- As with all loop analysis, we always break the loop at a high impedance node. The obvious choice is at the gate of M2.
3- Again, you do it as with all other loop analysis. Inject your 1V ac source after the break, and monitor the signal before the break!

 

[LvW]

Just two small comments to checkmates contribution:
* There is no other choice than to use the small signal modell since the loop gain per definition is a small signal parameter;
* palmeiras, before injection of a 1v test signal don`t forget to restore the proper bias at the gate of M2.

By the way, checkmate, I must confess you were right in assuming in the outer (overall) loop a positive loop gain below unity.
LvW

 

[checkmate]

No problem. We are all in this forums to learn.
Also, the threadstarter should attempt to compute both loop gain and the current equation given in the diagram (Note this is a large signal equation).

 

[palmeiras]

LvW, erikl and chemate,
Thank you very much, guys.

Erikl, your pdfs documents are useful. Thanks.

LvW and Checkmate,
I´ve written the small signal model for the circuit (neglecting output resistance of transistors), and I found loop gain equation proposed earlier by checkmate. The estimation provided by this equation is nearly equal to the simulated value (i. e. ~0.3 ) :-D. I broke the loop in the gate of M2 and check the signal before the break.

By the way, in order to finish our discussion,
What is the advantage to break the loop in the high impedance node? Could I break the loop in other nodes of the circuit? For instance, the drain node of M3?

Thank you very much,

 

[LvW]

By the way, in order to finish our discussion,
What is the advantage to break the loop in the high impedance node? Could I break the loop in other nodes of the circuit? For instance, the drain node of M3?

Palmeiras, the answer is simple:
For measuring/simulating the loop gain you must inject a test signal (therefore breaking the loop).
However, this must not alter the current/voltage ratio at any point or any node within the loop. Otherwise, the result is not applicable to the circuit to be analyzed.
In particular, the dc operating point must not be changed and the loading at this point must remain unchanged.
This leads to the rule of thumb for selecting a node where a small output resistance is connected to a large input resistance.
For opamp circuits this is preferably the opamp output. In the present case, the node with the highest input resistance is the gate of M2 (because of negative feedback through Rs). Therefore, this is the best node for our purpose to break the loop - and the error caused by fulfilling the above restriction not by 100% is negligible.
But, of course, the lost operating point (bias voltage at the gate of M2) has to be restored by an external dc voltage.

 

[palmeiras]

Hi LvW,
Thank you very much for your reply.

If possible, please, could you complete your above explanation?! It is not totally clear for me yet.
1) I cannot see how breaking the loop in this conditions (small output resistance + large input resistance), will mitigate the impact of breaking the loop, in terms of impedance. Do you have a suggestion for me to understand this rule?

2) You commented about circuits with amp. op. It is normal to break the loop at the output node. However, amplifiers often have high output resistance in order to increase the small signal gain. Am I correct or not?.
For example, differential pair with cascade devices or a folded cascade amplifier, present transistors with high values of output resistance. When in these cases, the amp. op output resistance is high, why is it proper to break the loop there?

3) When we are breaking a loop at some node, we always are changing the load conditions there. Am I correct or not?
So, the key point on your explanation is that "we should minimize the change of the impedance as much as we can". Did I get your message?

Obs: In the above circuit, I notice that the output resistance is low (1/gm1) and the input resistance is high (gate of M2).

Regards, Palmeiras.