This might be worse than a design that uses N priority encoders really. While you still clearly don't understand what I'm describing, it doesn't really matter as the book poses a better solution.
The original question didn't make it clear that "priority encoder" was one of the primitives that could effectively be written with behavioral modelling and that the structural part was the input/output modifications. As a result, my responses were focused on a generic structural coding of a priority encoder. The priority encoder that is based on an adder is one method that I know of that can do this. The goal is to use a trick to convert the arbitrary input to the priority encoder into a one hot input suitable for a simple encoder. From there, the logic for a simple encoder is the vector-and + or-reduce which can be constructed in a structural manner if needed, or with basic operators. But again, it sounds like "priority encoder" is being treated as a primitive /wrt this problem. You should ask your professor if the implementation of the generic priority encoder can be a behavioral implementation. Or maybe your book has an interesting example that shows a generic priority encoder and you should use that.
Also, saying N encoders is inefficient is not accurate. It is not area efficient. If N is small and the circuit needs to be fast, it is possible that the N encoder design would be justified. Likewise if N is small and area isn't a concern, N encoders could be justified as it is easier to write/verify.
--edit: the design of a priority encoder that needs to be generic and coded in a structural style and can't use codegen isn't a problem that should ever come up in a non-academic setting. If you need such an implementation, i'd go for the adder trick (-x) and (x) to convert the arbitrary input into a one-hot input. From there, you can use the vector-and followed by or-reduce, or you can do some generate tricks. I suspect this is not what the professor is looking for though, as the generic coding requires a fairly good understanding of Verilog/VHDL while also not aiding in teaching the core concept. It also is likely that the inappropriate coding style results in a worse design compared to the behavioral version.