Lock time depends on the BW and not on how the LPF is implemented. CP swing is limited both by CP bias margins and VCO's input voltage range again which does not depend on number of LPF poles and zeros.
You could aim for better phase margin but the complexity and constraints such a design brings in would make it not so useful.
You know, there is a compromise between these requirements and phase noise. So you have to decide which one come first. Generally designers favorites the low phase noise.