Problem with PLL which does not lock

[Sadegh.j]

Re: PLL Does not lock

Phase margin of about 60 degrees, locking time of less than 1 ps, rail to rail CP swing

 

[AdvaRes]

Re: PLL Does not lock

Phase margin of about 60 degrees, locking time of less than 1 ps, rail to rail CP swing

You can achieve the 60 deg phase margin. But, It is hard to have a 1 ps lock time.

 

[saro_k_82]

Re: PLL Does not lock

Lock time depends on the BW and not on how the LPF is implemented. CP swing is limited both by CP bias margins and VCO's input voltage range again which does not depend on number of LPF poles and zeros.
You could aim for better phase margin but the complexity and constraints such a design brings in would make it not so useful.

 

[Sadegh.j]

Re: PLL Does not lock

Thanks, I meant lock time of less than 1 ns. Sorry about the typo

 

[AdvaRes]

Re: PLL Does not lock

Thanks, I meant lock time of less than 1 ns. Sorry about the typo

You know, there is a compromise between these requirements and phase noise. So you have to decide which one come first. Generally designers favorites the low phase noise.

 

[Sadegh.j]

Re: PLL Does not lock

but the PLL has a low pass transfer function, and the phase noise gets weakened in the loop, right?