Problem with PLL which does not lock

[Sadegh.j]

Hi

I have designed a PLL that does not lock properly. All blocks work perfectly well, but the system does not lock. I know, it is probably the loop filter and I was wondering what to do with it.

Thanks

 

[mvs sarma]

when will pll not lock

Hi

I have designed a PLL that does not lock properly. All blocks work perfectly well, but the system does not lock. I know, it is probably the loop filter and I was wondering what to do with it.

Thanks

whether the loop filter is too broad? perhaps little more details are need like the pll chip used and a possible schematic of filter etc

 

[Sadegh.j]

pll loop not in lock

Hi

There is no chip. I am designing the chip my self. The loop filter is a simple pole and an RC zero, just as mentioned in the Razavi's CMOS book. May be this is what does not work .....

 

[safwatonline]

pll ns locking

i would say check the VCO

 

[Teddy]

pll charge pump pdf metastability

I am lost - are you simulating the pll or you bread-boarded one?
If simulating - you might not run long enough. It really takes a loong time to get it to lock. Little more info pls.

 

[AdvaRes]

pll locking problem

Hi

There is no chip. I am designing the chip my self. The loop filter is a simple pole and an RC zero, just as mentioned in the Razavi's CMOS book. May be this is what does not work .....

Hi,
Could you please post a figure showing Vc vs time ?

 

[Sadegh.j]

pll did not lock

I am simulating the PLL, and I am bread boarding nothing.

I am simulating the PLL for a long time, so no problem with this.

The VCo control voltage oscillates around its "correct" value for a some time, but drops to zero all of a sudden. The reason, I think is the loop filter, I will send the VCO control voltage soon.

Thanks

 

[AdvaRes]

phase margin vs lock time in pll

The VCo control voltage oscillates around its "correct" value for a some time, but drops to zero all of a sudden. The reason, I think is the loop filter, I will send the VCO control voltage soon.
Thanks

That's really strange.
I cant' say nothing regarding that unless I see Vc oscillation.

Waiting for your simulation result.
Cheers,
Advares

 

[Sadegh.j]

pll lock time simulation

Hi

I have attached the Vcontrol oscillation. The output is supposed to stay around 0.4v, but well, it does not.

Thanks

 

[Teddy]

pll can not lock

Hi,

well simulating PLL for just 60ns is surely not enough.
If you look at any comercial pll the lock time us in ms. I would guess that circuit is just getting to its initial state - not even close to lock.
I understand it takes a lot of simulation time but 60ns is surely not long enough. If you can run it for 1ms and to speed up the sims save perhaps just one or two nodes.

 

[AdvaRes]

pll not locking reasons

Hi,

well simulating PLL for just 60ns is surely not enough.
If you look at any comercial pll the lock time us in ms. I would guess that circuit is just getting to its initial state - not even close to lock.
I understand it takes a lot of simulation time but 60ns is surely not long enough. If you can run it for 1ms and to speed up the sims save perhaps just one or two nodes.

According to the figure It seems to be not a matter of simulation time.
Tryto permute the referance and the feedback signal at the input of the PFD.

Please let me know about the result.

 

[Sadegh.j]

pll is not locking

Teddy, I don't think it is the simulation time, the PLL theoretically can lock in less than 10 ns.

AdvaRes: What do you mean?

 

[AdvaRes]

pll not work

Teddy, I don't think it is the simulation time, the PLL theoretically can lock in less than 10 ns.

AdvaRes: What do you mean?

Hi Sadegh.j,

The PDF has two input rigth? : the clock reference and the feedback signal (the output of the frequency divider.
Simply try to permute their connection to the PFD.

 

[donmarino]

pll does not lock

pll lock time is greater then pll loop filter time constant. have you designed an rc filter with a pole around 1GHz?

 

[Sadegh.j]

pll dead zone

AdvaRes: I am doing clock oversampling as well, so I cannot simply do the permutation.

Donmarino: Why do you say this? The pole is at about 300Mhz, but the loop filter is the very well known loop filter using when you have a charge pump. Theoretically, the phase margin in 53 degrees. (MAtlab simulation)

Thanks guys

 

[Teddy]

PLL Does not lock

Looking at the picture - what is the target frequency?
How much current you dump to your loop filter - it seems you have huge ripple on the control voltage - in fact the ripple is about 10% of the control voltage - any VCO would go bananas.
and last - what is your PFD deadzone?

 

[Sadegh.j]

Re: PLL Does not lock

The circuit is supposed to work in 10Ghz, The ripple is huge, because the PLL is not locked. The dead zone is determined by the metastability of the flops. I do not think this is the reason though.
I pump 0.5mA into my loop filter.

Thanks

Added after 3 hours 11 minutes:

Ok, the PLL locked in 10Ghz and in 500ps. The problem was with the loop filter, and also with the one of buffers in my circuit. At the moment, the buffer is ideal though.

 

[mvs sarma]

Re: PLL Does not lock

The circuit is supposed to work in 10Ghz, The ripple is huge, because the PLL is not locked. The dead zone is determined by the metastability of the flops. I do not think this is the reason though.
I pump 0.5mA into my loop filter.

Thanks

Added after 3 hours 11 minutes:

Ok, the PLL locked in 10Ghz and in 500ps. The problem was with the loop filter, and also with the one of buffers in my circuit. At the moment, the buffer is ideal though.

Nice to know.

 

[Sadegh.j]

Re: PLL Does not lock

Thanks,

I am now looking for a more complicated loop filter structure, may be with two zeros and one pole, or two zeros and three poles, so I can have more freedom, any suggestions?

 

[saro_k_82]

Re: PLL Does not lock

Interesting.., What freedom you are looking for?