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problem simulation delay line

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yefj

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Hello , i was given a schematics which is supposed to be pulse delay .
my pulse is 3.3V and 220nS wide, but instead of a pulse on the outside i get a huge overshoot .
I know that LC system is a differencial equation which can lead to overshoot but its supposed to be a pulse delay.
Where did i go wrong?
LTspice file is attached.
Thanks.
1711374676646.png
 

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Hello Tony,you succseeded to do a huge delay in the line below. i tried to create a 3section network also, but i get only 12nS shift.
what is the mathematical logic behind such a large delay?

1712593378862.png


1712593411745.png

1712592906425.png
 
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Hello Tony, smaller pulse width ,smaller L smaller C.
How this works mathematickly?
Thanks.
 
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Elementary if you are a graduate. I assumed you were. Was I wrong?

ωo = 1/√(LC)

τd = √(LC) = 1/ ωo and maximally flat τd up to ωo using Bessel low Q filters.

So high BW causes low Tau. Doesn't that make sense.

Other filters have higher Q such as Butterworth (0.707) and more with Chebychev which have steep peak group delays at the poles near cutoff due to higher Q, yet your spectrum is weak there as it sets up the steeper cutoff. The lowest Cheby. PB ripple =0 dB filter then it becomes a Butterworth. This ghroup delay distortion also cause jitter in data pulses from distortion in eye patterns, so Gaussian or Raised Cosine or similar are used for continuous synchronous data pulses for low ISI (InterSymbol Interference.) Yet here you only assume 1 pulse.
 
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HelloTony, by the expression tau=69.5ns=0.069us so i need to multiply it by 3 in order to get the delay of the whole network?
correct?
Thanks.
1712603930224.png
1712603759190.png

--- Updated ---

UPDATE:
Hello Tony, If we build the sytem without the diode structure and i see a very big amplitue.
What is the logic of the structure you built to make the output resemble more of a pulse like shape.
Is there a name for such circuit?
Thanks.
1712604683868.png
 
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yefj said:
HelloTony, by the expression tau=69.5ns=0.069us so i need to multiply it by 3 in order to get the delay of the whole network?
correct?
Thanks.
View attachment 189917View attachment 189916
--- Updated ---

UPDATE:
Hello Tony, If we build the sytem without the diode structure and i see a very big amplitue.
What is the logic of the structure you built to make the output resemble more of a pulse like shape.
Is there a name for such circuit?
Thanks.
View attachment 189918
Click to expand...
You assumed BW from LC which is just for one stage or a 2nd order filter.
Cascaded filters are more complex in computation and might be done using matrices.
Can you see the difference cascading faster filters makes?
Lumped equivalent circuits for coax are infinite for 0 error, but sometimes 20th order delay lines are created.
For Audio, they just use a mechanical spring or a hallway.

We used to use 50 x 2 ns delay lines to measure data "Window Margin" to measure clocking errors by shifting early or late relative to PLL clock to measure bitshift with 2% resolution on 10MBaud datastreams in the 80's from the 1st 5.25 " HDD's to map disk defects, asymmetry, group delay distortion and timing defects.

Analog Oscilloscopes use delay lines to capture the signal with an early trigger so the delayed signal can be displayed.

But you seem to have unusual requirements for no purpose when you could use a digital clocked delay, if it is a synchronous pulse.

>(Diodes) Is there a name for such circuit?
How much electronics did you study?

It's a simple R-D "diode clamp that attenuates like a R-divider from the threshold voltage using V/I curve slope at If or the incremental resistance which limits to the fixed bulk resistance dependant on Rb~ 1/Pmax (est. +/-50%)

So ESD protection in CMOS once used 2 stages for 1 to 5 kV impulses to attenuate to 200 mV with high ESR low pF fast diodes. Now they used more complex active devices to clamp ESD in all CMOS logic with limits on energy.
 
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You're on the right track with your conjecture about LC time constant. I have run a variety of this kind of simulation. If all stages have identical LC values, then each stage adds the identical length of phase change.

Here are values demonstrating that ringing resonance starts at the first LC stage. Initial current charges the first C, which regurgitates the charge immediately back up to the inductors. The same process (governed by the LC time constant, looks like 0.7 mSec per stage) propagates a bit more delay with each LC stage.

delay contirbuted by each added LC stage 2000 Hz 5V.png
 
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BradtheRad said:
You're on the right track with your conjecture about LC time constant. I have run a variety of this kind of simulation. If all stages have identical LC values, then each stage adds the identical length of phase change.

Here are values demonstrating that ringing resonance starts at the first LC stage. Initial current charges the first C, which regurgitates the charge immediately back up to the inductors. The same process (governed by the LC time constant, looks like 0.7 mSec per stage) propagates a bit more delay with each LC stage.

View attachment 189919
Click to expand...
For 16th order Ladder filter with 8* 0.7 ms/stage = 5.6 ms delay, slightly more than 1/f but with significant attenuation using 10% of 200 Hz or a half pulse at 4kHz with a sqrt(LC) *Q = 1ms seems like 0.707 factor for a Ladder Filter per LC stage..

hmm Any Math experts on Filters here?

Group delay and phase delay - Wikiwand

In signal processing, group delay and phase delay are two related ways of describing how a signal's frequency components are delayed in time when passing throug...
www.wikiwand.com

I was wrong before in stating Group Delay from LC alone for breakpoint fo with frequency = 0 but with Q the impedance ratio for each stage. (?)

1712622488507.png


1712622215853.png
does not look right.

1712623345227.png
is the group delay near DC of f=0
 
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Hello,I am trying to build a single cell of delay as shown below , by the calculation i am supposed to get a 70ns=0.07usec delay between the pulses.
However when i zoom into the plot i dont see any move between them just a different rise time.
Why i cant see the 70ns shift between pulses?
Thanks.
1712688955048.png


1712689194966.png


1712688901876.png
 
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Hello,I have a pulse 0 -5V pulse which goes into a gate driver from hex inverter.This pulse needs to stay as close as possible to the original and be delayed by 1ms.
the pulse has 10ns of rise time/fall time and 500ns of pulse width.
hex invertor soure data sheet and gate driver which recieves the delayed pulse (in hope it will bu good enough to generate a clean pulse on the output of the gate driver)
I can just plug these two devices in the simulator because i have their spice model.
what are the strategy you reccomdn for the L-C values in each section and how many section to use?
Thanks.
74ABT04D

UCC5304DWVR
1715195449667.png
 
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It's completely unrealistic to implement the mentioned parameters (tpw 500 ns, trf 10 ns, td 1 ms) with a LC delay line. Digital pulse generation is most likely the best way.
 
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yefj said:
Hello,I have a pulse 0 -5V pulse which goes into a gate driver from hex inverter.This pulse needs to stay as close as possible to the original and be delayed by 1ms.
the pulse has 10ns of rise time/fall time and 500ns of pulse width.
hex invertor soure data sheet and gate driver which recieves the delayed pulse (in hope it will bu good enough to generate a clean pulse on the output of the gate driver)
I can just plug these two devices in the simulator because i have their spice model.
what are the strategy you reccomdn for the L-C values in each section and how many section to use?
Thanks.
74ABT04D

UCC5304DWVR
View attachment 190643
Click to expand...


What is the speed of light? 3e8 m/s = or 3e5 m/ms in air approx.
What distance is required to delay 1 ms on a common dielectric medium? = 200 km or 195 kilometers
What makes you think this is possible to transmit > 1MHz this distance or even with an LC simulation when you have been shown that BW is related to Gaussian maximally flat group delay with low Q values in either active or passive filters.

Even with a million stages, how long would it be with ideal parts?
Would they reach the stationary satellites in a daisy chain? When did you pass Physics 101? Time for a review. ( sarcasm filter off )

More important, why do you think this is a necessary design spec? Radar for space junk?
 
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No that is the wrong question for a designer. The datasheets define those answers.

The right question is to say “For this purpose and output function I need this characteristic. So define your “must have” sources or “givens, and output response.

Then define what is the problem.(s).

Anticipate all possible problems to be included in your design spec to be solved. If this is not possible then you are not ready to design it.
 
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Hello,I have found in the datesheet that the hex invertor which is the "signal generator" and for the reciever they say the following.
How do i define the source and load given the datasheets?
Thanks.


74ABT04D (pulse generator):
1715235500115.png



UCC5304DWVR: (receives the pulse)
1715237095175.png


1715237130138.png
 
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As expected, matched impedance on all interfaces for maximum bandwidth with rated capacitance in order to achieve guaranteed specs.

The includes Rt, CL & RL

1715257071100.png


the 5.5V logic family typically have a 50 ohm nominal output impedance, thus with a 50 pF rated load the rated rise time is Tau=RC= 2.5ns

If non-50 ohm traces or twisted pairs are used then ringing is possible from reflections, if the path round trip delay the rise time, so a std value 51 ohm + 33 pF were suggested to provide matching in the upper band to null reflections in that spectrum of the step pulse.

An analog spectrum for a pulse is often measured or computed as follows: f-3dB=0.35/Tr (10~90%)
Yet 1st order LPF is taken from the exponential step response 0 to 63% of target level which resolves to BW= 208 MHz and not 10 to 90% value yet a comparator set to 50% will be faster and compute a high toggle rate.

So the equation for maximum toggle frequency or minimum pulse width, depends on the thresholds, which are typically 0 to 50%.

We know that matched impedances eliminate reflections but also attenuate output 50% so a 250 ohm load to Vext/2 is the compromised Thevenin equiv. for this logic level driver for both SNR and BW. The two 500 ohm R's would mean only for that criteria, the load is 250 Ohms. SNR meaning signal/noise ratio for the unknown noise. SNR and BW are directly related to Shannon's Law and the Shannon Hartley Theorem for probability of errors.

Yet your phantom pulse project used 1.2uH+40 Ohms with negative feedback on R so it becomes a high impedance current source mismatched to everything. That's why it must be placed near the coil to avoid round trip prop delay> rise time. The open loop BW with feedback must meet or exceed the modulator's closed loop BW spec and meet the SNR required for resolution and signal quality. You must work backwards to determine SNR from the project requirements with additional margin for unknowns. This is why design specs are far more important than picking parts by trial and error.

Now you know that 5V logic families are all 50 ohm Ohm (Vol/Io = Z nominal) +/-33% typ.) and this risetime indicates a toggle frequency of 200 MHz is maybe possible. Now 3.6V max logic families are about 22 to 25 Ohms with the same wide tolerance and thus can go faster but typically operate at 3.3V and used in CMOS everywhere. There may be some exceptions but a standard family is the 74ALC and some uC rated for 3.6V max. The 74ABT is in the older 5.5V family and the T just means it is TTL input or 2 Si diode levels of Vf for the nom. input threshold. There are dozens of logic families as smaller lithography made devices faster. But they standardized Impedance or RdsOn at nominal rate voltage max for families like 5.5V, 3.6V and now lower levels with even lower Vol/Io = RdsOn such as in 1V CPU logic to achieve GHz speeds with lower gate capacitance too. If you know RdsOn characteristics for any FET then this will make sense to avoid shootthru high currents in CMOS, thus the Vt thresholds will determine the dynamic RdsOn and Coss during transition and ideally you want this constant but in CMOS this is imperfect due to tolerances. The device characteristics with lower RdsOn FETs also have higher Coss or Cout unless made smaller by lithography or SiC or GaN. This is also why some standards like impedance are never specified in datasheets , but implied if you compute Vol/Io, then you will understand why it must be standardized for speed and shoot-thru supply drawn current-noise reasons which create noise on Vdd unless suppressed by design.
 
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