Preventing antenna effect in IC layout design

[erikl]

Only on applied layers (poly, metal & insulation layers), not on inserting processes (implants, diffusions).

 

[dick_freebird]

RIE is used for many removals (shallow trench, active, poly,
all the way up) but you don't care about layers below the
gate oxide or layers that are nonconductive (although ones
like via, etching ILD, can hit the conductor as the etch bottoms
out).

RIE has nothing to do with implants, other than as a hard-mask
predecessor step.

 

[vijayaganesh]

thanks erikl and dick_freebird.i jst got it.but i hav little doubt in that ..plz clarifies me.still now i m thinking every layers in cmos can happen step by step procedure during fab, so i know the process .my doubt is first m1 then m2 them m3.....like this process only the layers got deposited ....for every metal layer deposition there is etching happens? plz correct me if i am wrong!

 

[erikl]

....for every metal layer deposition there is etching happens?

Yes, that's correct. Also for poly layer(s).

 

[Sathe esh]

that ....my question is ....does the reactive ion etching process happens on implant of every layers (i.e.poly diff,well,m1,m2.....etc)?

The Etching process has to be done after every layer deposition. And you will get the exact layout representation after the etching process. The Reactive ion etching is just one of the mehods like wet &, plasma etching..