Bandgap is overkill for POR, maybe useful for more accurate
UVLO spec. The POR is for forcing known states earlier than
when detail specs apply.
For a raw threshold I like a resistor loaded FET stack of 1 N
and 1 P from Vdd to a N gate, N drain via load res to Vdd,
take that to any buffering you like. Virtues are simplicity and
no externalities besides Vdd to meddle.
Getting logic sorted before anyhing can hog current (maybe
defeating the power-up entirely, in hiccup-mode startup
schemes) is key. An N and P VT sum is pretty good for that.
You might even play with multiple supply-level-detects if
you have bunches of circuitry that "start waking up" at
different levels and want different power switch-on or
activity switch-on points.
Untangle the reset, power management and functional UVLO
if any, and build up from simplest, getting fancy probably
leads you astray, when the goal is "everything under some
kind of control, as early as possible" - functions which need
a lot of headroom are not your friend, for this.