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POR circuit design

darksteez

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Hi, I've been trying to design a POR circuit with some given electrical characteristics like supply current, threshold for rising VDD, falling VDD, Hysteresis, RESETB pulse width etc. This is kind of my first full-fledged small DIY project, so I'm a bit noob pls bear :(
I read various papers about POR circuits and all and have made some basic notings, like I mainly saw 2 architectures for designing a POR circuit, with one involving resistor divider + BGR+ comparator and another one involving some buffers and stuff. I've decided to move on with the first method, I understood the basic workings of the circuit, and started designing a BGR but I'm facing a lot of issues. Can any of you guys, guide me through this on how I go about designing stuff to match my specifications? I cant figure out the path to follow.
PS I'm using 65nm CMOS process.
 
Can you give a little bit more details about the issues you are facing? Also, attach plots of the output of the bandgap voltage and supply voltage.
 
Bandgap is overkill for POR, maybe useful for more accurate
UVLO spec. The POR is for forcing known states earlier than
when detail specs apply.

For a raw threshold I like a resistor loaded FET stack of 1 N
and 1 P from Vdd to a N gate, N drain via load res to Vdd,
take that to any buffering you like. Virtues are simplicity and
no externalities besides Vdd to meddle.

Getting logic sorted before anyhing can hog current (maybe
defeating the power-up entirely, in hiccup-mode startup
schemes) is key. An N and P VT sum is pretty good for that.
You might even play with multiple supply-level-detects if
you have bunches of circuitry that "start waking up" at
different levels and want different power switch-on or
activity switch-on points.

Untangle the reset, power management and functional UVLO
if any, and build up from simplest, getting fancy probably
leads you astray, when the goal is "everything under some
kind of control, as early as possible" - functions which need
a lot of headroom are not your friend, for this.
 

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