Placement of bypass capacitor

[kripacharya]

okay... but the text explains how the multi-plates inside the cap now go edge-on to the power planes & hence reduce the capacitance, with the end mounting method. The inductance on the ends wouldn't change i think.

 

[Funkehed]

I want to bring up this topic again.
I am working on 4 layer PCB right now and getting to decoupling of TQFP microcontroller and TQFP CPLD.
Everybody agrees that placing a decoupling cap on the same layer as a power pin and placing vias on the opposite side of the pads of the cap (not between the cap and the power pin) is the best way to go. But this approach is not possible for layouts with BGA or when decoupling caps placed on the other side of the board. Every via will connect a power pin to internal planes before it goes to a pad of a cap, which decrease efficiency of the decoupling.

I plan to place my decoupling caps on the bottom. But I was thinking about one trick which could improve the decoupling. So, I want to disconnect the vias between the power/ground pins (the top ones on the pic) and the pads of the cap from the internal planes. This way the current will flow from the internal plane to the pad, then from the bottom to the top (avoiding internal planes), and then to the pin. It increases the size of the loop and still have the inductance of the via, but it somehow resembles the "same-layer" solution.



What do you think about this trick?

 

[swen_s]

I have found this document (it has the same picture I found with google)

Figure 1a is the best way he says.

http://www.sigcon.com/Pubs/news/9_07.htm

But what happens if you move the capacitor (in figure 1a) closer to the pin so both vias is on the same spot? This would be the best if it is possible?

 

[marce]

Place your caps on the bottom side under the IC pins (this uses dead PCB area and gives you more space) and via out from the IC and use the same pins for the cap. As the power plane capacitance is used first then the bypass cap recharges this, this would give you the best option and use the minimum board space. What you are proposing is not correct, as said the power planes supply the initial charge, the decoupler replenishes this charge, don't overcomplicate your design.

 

[Ice-Tea]

Just to add my ,02$...

I took a high speed/signal integrity seminar that pretty much seconded what Marce said: via in between IC and decoupling cap. The reasoning being that the interplane capacitance is the 'first line of defense', the sooner you 'get' to it the better. Off course, that only makes sense if you have interplane capacitance. I would imagine that on a 2 layer 1.6mm PCB with tracks making up the power 'planes' this discussion becomes null and void. That said, I suppose high speed designs and 2 layer PCBs don't mix all that well to begin with

 

[Funkehed]

Thank you, marce and Ice-Tea.
I should pay more attention to the inter-plane capacitance.
I implemented this approach in a previous revision of the design, but I was not sure because some of the Tech Notes treat this approach as bad practice.

The factor of the inter-plane capacitance now puts me in front of one small dilemma.
A power rail for a FPGA in my design is separated form the main power rail by a ferrite bead, this makes the effective inter-plane capacitance smaller due to a smaller area of the power plane under CPLD.
For larger inter-plane capacitance the overlapping area between the planes must be larger. The main power plane is powered by an LDO, but I have several DC-DC switches on the board.
I am trying to understand what will give me more benefits:
- smaller power plane under the FPGA and a ferrite bead;
- large power plane and no ferrite bead?

Sorry for the offtopic.

 

[Ice-Tea]

Beads or no beads is another discussion wherr there are no simple answers and no clear winners and loosers. To be honnest, for me personally beads have more often been part of a problem rather than the solution. I often don't bother, especially not with purely digital system parts.

 

[Funkehed]

The sequence of my thoughts was as following;
- I am implementing decoupling caps on the other side of the boards;
- I need larger inter-plane capacitence;
- but I have a bead which separate the CPLD power plane from a large main power plane, therefore the inter-plane capacitance is smaller for CPLD;
So I had to choose: large inter-plane capacitance or a ferrite bead. From what you are saying it is not much of a benefit of using a bead, so I will probably choose a large power plane.

 

[marce]

What you describe describes high speed layouts with FPGA's CPLD's DDR memory, I do quite a few every year and have been doing these sort of designs for over a decade now. Do the best you can but don't get over worried about the inter plane capacitance, I often do boards with numerous power islands (separated by either a ferrite or an LDO), I try to place the capacitors as best as I can constrained by the design, but you must remember ALL PCB design is a compromise, otherwise we would never get boards out of the door, so aim for the best, but don't worry to much about the very finite details. When I do have to worry about power to such an extent, it is time to use power delivery system simulation software.
I don't know what system you use for layout, but all the main ones do have PDS simulation add ons, it may be worth you investigating this software, it is quite interesting to use and see the results for actual boards, though it may shock you:grin:
Another thing worth looking at is how you can achieve higher interplane capacitance with HDI PCB design, which I think gives the best usage of space and the best ELECTRICAL environment for signals.