PI controller effect on the DC of error signal in PLL

[yefj]

Hello,I have built a PI controller I have its time domain step responce and AC responce.
PI controller is supposed to help with the DC part of the error signal of a PLL system.
I cant undertnad how,Is there away i could see it?
Thanks.

 

[FvM]

You don't see integral part of controller response with a short non-zero pulse. Need to increase pulse width at least to ms scale.

 

[yefj]

Hello FVM, when I increased the pulse to 1ms I got a tottaly difference responce shown below. I marked by red arrows small oscilations.
I know that in PLL system a PI controller is influencing the DC part of the error signa coming out of a phase detector.
Where can I see this "DC" influence in the responce below?
Thanks.

 

[dick_freebird]

Integral term in negative feedback removes
DC error over long time. It removes any bias
(gain error and offset error) of the Proportional
path. This is "fine settling time", though. The
coarse settling time is in the Proportional.

Derivative, which you neglect, would help with
the overshoot if scaled properly to the natural
response of the bigger picture and the amp.
It removes Proportional slew required, before
Proportional and Integral "wake up" and mis-
respond to the HF / high-dV/dt component.

 

[yefj]

Hello dick_freebird,With my previos amplifier i got the error signal to be much less pk-pk value.
However the error signal had constant change in mean value going in one direction.
I see gradual change in mean value at some rate as the time passes.

Is there a way I could simulate how the PI controller will change the DC mean value of the error signal ?
Thanks.

 

[D.A.(Tony)Stewart]

Stop using the LT1028. It has terrible overshoot

 

[yefj]

When the phase shift is 90 degrees then error is zero.I can reach this point by tuning into the exact resonance and doing phase shift of 90 degrees by tuning the phi 2 phase shifter.
Its almost what I have done in the videos below.

The main issue is the controller .
There is a PI controller I have simulated.
Is there a way I could see its effect on my error signal?
My error signal is suffering from DC drifting over time.
Thanks.


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[D.A.(Tony)Stewart]

It is hard to understand your videos because I do not recognize which elements on the block diagram are the physical objects and if your actual schematic is performing as expected. Also you are assuming we recognize your setup where the physical layout does not match the block diagram.

The servo block diagram has a partial integrator with series R to limit the attenuation. Then the steady state error voltage should always be zero unless your reference in the DBM mixer changes or the DBM drifts or the YIG is drifting with self-heating , the latter being the most likely scenario.

Do you have an oven to stabilize the YIG oscillator to less than 0.01 'C?

The varactor diode and other temperature sensitive servo control elements will also require an oven to keep at constant temp within 1'C.

 

[yefj]

Hello Tony , I will try and put the yig exactly on the resonance of the cavity resonator .
After that I will make 90 degrees phase shift at that point so the error signal will be zero .
In theory in resonance there is a sudden change of phase so I will see the error signal going from positioned to negative .

The key this that I am missing is how to interpret the simulation of the PI controller into the effect it will do on the error signal .
Pi controller AC response has a shape like slope going doing and then steady state in the gain .
How PI affect the DC drift in PLL?
Is there some mathematical intuition I could use ?
Thanks .

 

[dick_freebird]

There are many videos and tutorials out there
about tuning PID control loops. These probably
explain it better than we will.

I imagine that if you understand this, what
your circuit wants will become clear (or the
process of tuning may sort it, itself).

 

[FvM]

I don't think that PI controller is the critical part of the design. It's most likely adjustment and stability of carrier supression feature. If not setup correctly, the phase detector input signal is dominated by circulator crosstalk instead of wanted resonator reflection.

 

[D.A.(Tony)Stewart]

You need to validate every component function matches the description in the reference paper and that includes thermal oven stabilization and carrier suppression measurement. The PI integrates the output in the DBM. The DBM multiplies to compute the phase voltage shift. If your mixer is not linear then find out why. If your phase shift is not linear then calibrate it . Calibrate every part so the system works rather than what you seem to be doing. You have enough tools to do this with stable RF generators. The open loop condition when close within DBM BW will show your mixer linearity with a signal. Measure it with two stable generators then use an FM input to scale and test your PI controller. If you don't have access to these ports, you did not design it for testability (DFT).

 

[FvM]

To understand possible trapdoors of the complex system, it makes sense to review the initial discussion one year ago: https://www.edaboard.com/threads/strategy-for-designing-a-locking-component-in-pll.409364
and specifically the original IEEE paper describing the design: Amitava Sen Gupta, David A. Howe, Craig Nelson, Archita Hati, Fred L. Walls andJoseF.Nava High Spectral Purity Microwave Oscillator: Design Using Conventional Air-Dielectric Cavity
Reprints are publically avalaible, e.g. here

https://tf.nist.gov/general/pdf/1887.pdf

 

[yefj]

UPDATE:
My system is a frequency locked loop, by the diagram bellow, I intend to make a plot of a frequency Vs error signal as shown below.
Given this plot how would it help me to know the controller parameters I should use when building the controller?
Thanks.

 

[FvM]

The plot gives a single parameter "detector gain". To design a controller, you need also VCO gain and dynamic behaviour (bandwidth respectively delay) of VCO and detector.

Other than assumed by your sketched red lines, the detector transfer curve isn't necessarily monotonic outside useful range, or do you see monotonic behaviour when tuning VCO?

 

[yefj]

Hello FVM , so I need to do three plots:
1.error voltage vs. frequency (A vs B in the digram)
we dont use VCO in this stage(purely signal generator in A input ,recored output in B)
2. Vco gain I assume its recording the input of the VCO(output of the controller) and reccording the output signal? correct?
I will try and wait till the YIG will stop drifting altough it take time for the coils to stabilize thermally.
YIG has two coils, the tune coil is very large and I put DC voltage so the YIG will be in the area of the resonance and the FM coil which is smaller but i think it also needs to stabilise so i will put some current threw it to make it warm and steady state thermally.

3."dynamic behaviour (bandwidth respectively delay) of VCO and detector"
coulyou please explain how i measure BW and delay of VCO(YIG) and detector(mixer)?
Thanks.

 

[yefj]

Hello , I plugged a signal generator into point A of my system(as shown in the diagram and reccorded the error signal voltage which comes out from the mixer(POINT B).The plot below is based on crude manual point writing .At 9518Mhz we have error 0mV , there is a frequency range shown in red arrow where we have linear dependancy between frequency and error.
After the red frequency range the error behaves the opposite, exactly in the diagram photo below.
Matlab code is attached.

What steps do I need to do next to know what kind of PID condtroller behavior should i use for locking?
Video of the setup and measurment is attached in the link.

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freq_up=[9516.89,9517.6,9517.69,9517.81,9517.83,9517.86,9517.9,9518,9518.05,9518.07,9518.1,9518.13,9518.18,9518.33,9518.45,9518.68,9519.01,9520.3]
error_up=[40,47,52,31,26,13,3,-0.4,-3.7,-8.3,-13.5,-25,-39,-35,-30,-24,-18,-1]
plot(freq_up,error_up)
xlabel('frequency [MHz]')
ylabel('error signal mixer phase detevtor[mV]')