Photo diode with basic circuit

[heena123]

hi,

I go through this given link...from that i am assume that for my signal logic high level (high=1)is may be minimum 3.7V & logic low level(low =0) is may be higher 1.3V.

But i have to ask one question ,"My controller is works on 3.3V VCC supply so for it what is the high & low voltage level ?"

In this link it is given for 5 V Vcc supply for CMOS family.

Please clarify my confusion .


One microsecond is a very short time for a train of devices to detect. That is the reason it pays to reduce any slack in activation times, in the sense that you want to hook up the diode so that it's per-biased to the threshold of responding, and furthermore to construct your op amp circuit so it responds as quickly as possible.

I didn't get the meaning of your above sentence.


Thank You

 

[BradtheRad]

Since your device works on 3.3V, it should recognize 2.45V as high.

The other half of the job is you must also determine the region where it will recognize a low.

As for my statement, it has to do with the necessity for you to minimize the total response time of your entire circuit.

I have seen a spec saying the 741 op amp has a slew rate of .5V per microsecond. This means it will take a few microseconds to show sufficient rise at the output pin, in order for your pic to recognize a change in logic state.

The 741 may not be fast enough to suit your purposes. You may need a premium op amp to do the job. (And a transistor may turn out to be able to be the fastest device to do the job.)

Regardless, you will still need to eliminate all causes that can slow down the response. Some causes are eliminated by the usual guidelines we hear about.

Other guidelines need your particular attention and creative thinking.

A partial list of guidelines includes:

* Use the shortest lengths of wiring between your devices as you can.

* Reduce all stray capacitances. There is probably more than one place this needs to be done.

* Find a way to adjust your photodiode bias in quiescent mode so that it's at the brink of turning on. That way it will respond immediately (or most rapidly) to a flash of the laser.

* Adjust your op amp network so the output is a little above 0 V in quiescent mode. That way it needs to travel less distance to switch to high.

Etc.

 

[thylacine1975]

Hi guys!

I see BradTheRad is giving piles of useful information so I won't attempt to add to the detail... oh OK - a good rule of thumb is that for CMOS circuits [which your 3.3V stuff will most certainly be] the logic threshold is ~Vcc/2 : i.e. > 1.7 V = high, < 1.5 V = low. Noise margin etc notwithstanding

As you've no doubt discovered, there are many possible flavours/solutions when designing photodetectors. Which one you use depends primarily on whether optimisation for speed, sensitivity or noise is your goal. Since you're using photodiodes, have a peek at the Wikipedia page Photodiode - Wikipedia, the free encyclopedia since it covers the both the photoconductive and photovoltaic modes of operation (which is governed by a) your circuit, and b) the applied bias).

If you're trying to build lab photodetectors, there is a paper covering a couple of topologies that might be useful:
http://www.0x00f.com/files/appnotes/photodetctor-designs.pdf
(Since it was written 13+ years ago, the devices it refers to are getting old, but the discussion is still valid)

I wrote a [humorous] guide to rolling your own photodetector a few years back that might also help (...or at least provide a smile - if I've figured out how to attach the file correctly!)
View attachment 1 hour photodetector.pdf

Good luck!