Phase detection mechanism

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promach

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If https://github.com/promach/DDR/blob/main/phase_detector.v is used to help with clocK-Centering calibration activity in Figure 17-20, I have a concern that it would not work for the data signal D2.

there is ambiguity on whether to move D2 to the left or to the right
The direction (left or right) is dependent on D0 and D1 (at least few other signals have to be compared with D2)

Do you have any comment about calibrating D2 in this case ?

Besides, any idea why only slave is calibrated here ?
 

now, I am checking if I could eliminate either cal_master or cal_slave signal since I am only using one single whole deserializer

I suspect the same phase calibration mechanism could be done without using an extra SLAVE ISERDES

 

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