Phase detection mechanism

[promach]

1) Do anyone know how this https://github.com/promach/DDR/blob/main/phase_detector.v works internally ?

2) What does it mean by MAX in Figure 9 of XAPP1064 appnote ?

3) Could anyone explain what it means by Early Data Sampling and Late Data Sampling ?

4) As for why is it 5 bits wide for pdcounter , someone told me that the verilog code only supports 32 (which is equivalent to 2⁵) steps, but that is 1/8 of the total possible delay steps (256 delay taps) ?

 

[promach]

If https://github.com/promach/DDR/blob/main/phase_detector.v is used to help with clocK-Centering calibration activity in Figure 17-20, I have a concern that it would not work for the data signal D2.

there is ambiguity on whether to move D2 to the left or to the right
The direction (left or right) is dependent on D0 and D1 (at least few other signals have to be compared with D2)

Do you have any comment about calibrating D2 in this case ?

Besides, any idea why only slave is calibrated here ?

 

[promach]

There seems to be some text explanation at https://www.xilinx.com/support/documentation/user_guides/ug381.pdf#page=82 and https://www.xilinx.com/support/documentation/white_papers/wp249.pdf#page=5 , but I am still reading.

 

[promach]

now, I am checking if I could eliminate either cal_master or cal_slave signal since I am only using one single whole deserializer

I suspect the same phase calibration mechanism could be done without using an extra SLAVE ISERDES